Simulation Results: sram_ctrl

 
25/11/2025 16:03:05 sha: 3424e7f json Branch: master Tool: vcs [unknown]
Coverage statistics
  • score
  • 93.96
  • line
  • 98.33
  • cond
  • 91.55
  • toggle
  • 90.66
  • fsm
  • 90.48
  • branch
  • 95.71
  • assert
  • 95.09
  • group
  • 95.92
Validation stages
V1
100.00%
V2
100.00%
V2S
70.83%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
sram_ctrl_smoke 62.810s 2179.627us 1 1 100.00
csr_hw_reset 1 1 100.00
sram_ctrl_csr_hw_reset 0.770s 34.189us 1 1 100.00
csr_rw 1 1 100.00
sram_ctrl_csr_rw 0.850s 21.490us 1 1 100.00
csr_bit_bash 1 1 100.00
sram_ctrl_csr_bit_bash 1.140s 48.843us 1 1 100.00
csr_aliasing 1 1 100.00
sram_ctrl_csr_aliasing 0.920s 35.945us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
sram_ctrl_csr_mem_rw_with_rand_reset 0.910s 93.781us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
sram_ctrl_csr_rw 0.850s 21.490us 1 1 100.00
sram_ctrl_csr_aliasing 0.920s 35.945us 1 1 100.00
mem_walk 1 1 100.00
sram_ctrl_mem_walk 8.980s 2508.213us 1 1 100.00
mem_partial_access 1 1 100.00
sram_ctrl_mem_partial_access 2.500s 225.181us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
multiple_keys 1 1 100.00
sram_ctrl_multiple_keys 619.520s 24711.255us 1 1 100.00
stress_pipeline 1 1 100.00
sram_ctrl_stress_pipeline 156.070s 10309.651us 1 1 100.00
bijection 1 1 100.00
sram_ctrl_bijection 18.440s 1567.517us 1 1 100.00
access_during_key_req 1 1 100.00
sram_ctrl_access_during_key_req 45.830s 225.184us 1 1 100.00
lc_escalation 1 1 100.00
sram_ctrl_lc_escalation 3.850s 982.060us 1 1 100.00
executable 1 1 100.00
sram_ctrl_executable 165.220s 6707.074us 1 1 100.00
partial_access 2 2 100.00
sram_ctrl_partial_access 5.130s 729.188us 1 1 100.00
sram_ctrl_partial_access_b2b 95.660s 5398.991us 1 1 100.00
max_throughput 3 3 100.00
sram_ctrl_max_throughput 1.910s 40.409us 1 1 100.00
sram_ctrl_throughput_w_partial_write 20.960s 480.708us 1 1 100.00
sram_ctrl_throughput_w_readback 64.600s 297.869us 1 1 100.00
regwen 1 1 100.00
sram_ctrl_regwen 70.480s 1611.622us 1 1 100.00
ram_cfg 1 1 100.00
sram_ctrl_ram_cfg 0.920s 30.617us 1 1 100.00
stress_all 1 1 100.00
sram_ctrl_stress_all 1982.920s 393562.173us 1 1 100.00
alert_test 1 1 100.00
sram_ctrl_alert_test 0.980s 36.535us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
sram_ctrl_tl_errors 1.870s 29.333us 1 1 100.00
tl_d_illegal_access 1 1 100.00
sram_ctrl_tl_errors 1.870s 29.333us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
sram_ctrl_csr_hw_reset 0.770s 34.189us 1 1 100.00
sram_ctrl_csr_rw 0.850s 21.490us 1 1 100.00
sram_ctrl_csr_aliasing 0.920s 35.945us 1 1 100.00
sram_ctrl_same_csr_outstanding 1.050s 68.519us 1 1 100.00
tl_d_partial_access 4 4 100.00
sram_ctrl_csr_hw_reset 0.770s 34.189us 1 1 100.00
sram_ctrl_csr_rw 0.850s 21.490us 1 1 100.00
sram_ctrl_csr_aliasing 0.920s 35.945us 1 1 100.00
sram_ctrl_same_csr_outstanding 1.050s 68.519us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
passthru_mem_tl_intg_err 1 1 100.00
sram_ctrl_passthru_mem_tl_intg_err 2.050s 287.190us 1 1 100.00
tl_intg_err 1 2 50.00
sram_ctrl_tl_intg_err 1.600s 756.983us 1 1 100.00
sram_ctrl_sec_cm 0.790s 6.757us 0 1 0.00
prim_count_check 0 1 0.00
sram_ctrl_sec_cm 0.790s 6.757us 0 1 0.00
sec_cm_bus_integrity 1 1 100.00
sram_ctrl_tl_intg_err 1.600s 756.983us 1 1 100.00
sec_cm_ctrl_config_regwen 1 1 100.00
sram_ctrl_regwen 70.480s 1611.622us 1 1 100.00
sec_cm_readback_config_regwen 1 1 100.00
sram_ctrl_regwen 70.480s 1611.622us 1 1 100.00
sec_cm_exec_config_regwen 1 1 100.00
sram_ctrl_csr_rw 0.850s 21.490us 1 1 100.00
sec_cm_exec_config_mubi 1 1 100.00
sram_ctrl_executable 165.220s 6707.074us 1 1 100.00
sec_cm_exec_intersig_mubi 1 1 100.00
sram_ctrl_executable 165.220s 6707.074us 1 1 100.00
sec_cm_lc_hw_debug_en_intersig_mubi 1 1 100.00
sram_ctrl_executable 165.220s 6707.074us 1 1 100.00
sec_cm_lc_escalate_en_intersig_mubi 1 1 100.00
sram_ctrl_lc_escalation 3.850s 982.060us 1 1 100.00
sec_cm_prim_ram_ctrl_mubi 1 1 100.00
sram_ctrl_mubi_enc_err 1.230s 40.632us 1 1 100.00
sec_cm_mem_integrity 1 1 100.00
sram_ctrl_passthru_mem_tl_intg_err 2.050s 287.190us 1 1 100.00
sec_cm_mem_readback 0 1 0.00
sram_ctrl_readback_err 0.840s 25.715us 0 1 0.00
sec_cm_mem_scramble 1 1 100.00
sram_ctrl_smoke 62.810s 2179.627us 1 1 100.00
sec_cm_addr_scramble 1 1 100.00
sram_ctrl_smoke 62.810s 2179.627us 1 1 100.00
sec_cm_instr_bus_lc_gated 1 1 100.00
sram_ctrl_executable 165.220s 6707.074us 1 1 100.00
sec_cm_ram_tl_lc_gate_fsm_sparse 0 1 0.00
sram_ctrl_sec_cm 0.790s 6.757us 0 1 0.00
sec_cm_key_global_esc 1 1 100.00
sram_ctrl_lc_escalation 3.850s 982.060us 1 1 100.00
sec_cm_key_local_esc 0 1 0.00
sram_ctrl_sec_cm 0.790s 6.757us 0 1 0.00
sec_cm_init_ctr_redun 0 1 0.00
sram_ctrl_sec_cm 0.790s 6.757us 0 1 0.00
sec_cm_scramble_key_sideload 1 1 100.00
sram_ctrl_smoke 62.810s 2179.627us 1 1 100.00
sec_cm_tlul_fifo_ctr_redun 0 1 0.00
sram_ctrl_sec_cm 0.790s 6.757us 0 1 0.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
sram_ctrl_stress_all_with_rand_reset 23.180s 2028.621us 1 1 100.00