Simulation Results: uart

 
25/11/2025 16:03:05 sha: 3424e7f json Branch: master Tool: vcs [unknown]
Coverage statistics
  • score
  • 87.56
  • line
  • 99.17
  • cond
  • 96.38
  • toggle
  • 91.55
  • fsm
  • None
  • branch
  • 96.97
  • assert
  • 95.97
  • group
  • 45.33
Validation stages
V1
100.00%
V2
94.12%
V2S
100.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
uart_smoke 8.820s 6155.517us 1 1 100.00
csr_hw_reset 1 1 100.00
uart_csr_hw_reset 0.600s 50.951us 1 1 100.00
csr_rw 1 1 100.00
uart_csr_rw 0.740s 11.769us 1 1 100.00
csr_bit_bash 1 1 100.00
uart_csr_bit_bash 2.170s 351.667us 1 1 100.00
csr_aliasing 1 1 100.00
uart_csr_aliasing 0.920s 28.418us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
uart_csr_mem_rw_with_rand_reset 0.660s 21.485us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
uart_csr_rw 0.740s 11.769us 1 1 100.00
uart_csr_aliasing 0.920s 28.418us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
base_random_seq 1 1 100.00
uart_tx_rx 9.240s 61730.012us 1 1 100.00
parity 2 2 100.00
uart_smoke 8.820s 6155.517us 1 1 100.00
uart_tx_rx 9.240s 61730.012us 1 1 100.00
parity_error 2 2 100.00
uart_intr 32.830s 34799.011us 1 1 100.00
uart_rx_parity_err 135.950s 127142.721us 1 1 100.00
watermark 2 2 100.00
uart_tx_rx 9.240s 61730.012us 1 1 100.00
uart_intr 32.830s 34799.011us 1 1 100.00
fifo_full 1 1 100.00
uart_fifo_full 11.610s 35876.965us 1 1 100.00
fifo_overflow 1 1 100.00
uart_fifo_overflow 92.760s 97627.506us 1 1 100.00
fifo_reset 1 1 100.00
uart_fifo_reset 30.430s 44085.530us 1 1 100.00
rx_frame_err 1 1 100.00
uart_intr 32.830s 34799.011us 1 1 100.00
rx_break_err 1 1 100.00
uart_intr 32.830s 34799.011us 1 1 100.00
rx_timeout 1 1 100.00
uart_intr 32.830s 34799.011us 1 1 100.00
perf 1 1 100.00
uart_perf 271.280s 14429.808us 1 1 100.00
sys_loopback 1 1 100.00
uart_loopback 2.830s 1753.925us 1 1 100.00
line_loopback 1 1 100.00
uart_loopback 2.830s 1753.925us 1 1 100.00
rx_noise_filter 0 1 0.00
uart_noise_filter 4.630s 7613.074us 0 1 0.00
rx_start_bit_filter 1 1 100.00
uart_rx_start_bit_filter 1.650s 656.041us 1 1 100.00
tx_overide 1 1 100.00
uart_tx_ovrd 19.860s 7134.277us 1 1 100.00
rx_oversample 1 1 100.00
uart_rx_oversample 26.400s 7359.444us 1 1 100.00
long_b2b_transfer 1 1 100.00
uart_long_xfer_wo_dly 158.820s 296723.023us 1 1 100.00
stress_all 0 1 0.00
uart_stress_all 90.100s 238217.654us 0 1 0.00
alert_test 1 1 100.00
uart_alert_test 0.830s 24.304us 1 1 100.00
intr_test 1 1 100.00
uart_intr_test 0.730s 47.244us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
uart_tl_errors 1.640s 101.113us 1 1 100.00
tl_d_illegal_access 1 1 100.00
uart_tl_errors 1.640s 101.113us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
uart_csr_hw_reset 0.600s 50.951us 1 1 100.00
uart_csr_rw 0.740s 11.769us 1 1 100.00
uart_csr_aliasing 0.920s 28.418us 1 1 100.00
uart_same_csr_outstanding 0.780s 16.422us 1 1 100.00
tl_d_partial_access 4 4 100.00
uart_csr_hw_reset 0.600s 50.951us 1 1 100.00
uart_csr_rw 0.740s 11.769us 1 1 100.00
uart_csr_aliasing 0.920s 28.418us 1 1 100.00
uart_same_csr_outstanding 0.780s 16.422us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
uart_tl_intg_err 1.100s 90.760us 1 1 100.00
uart_sec_cm 1.000s 322.349us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
uart_tl_intg_err 1.100s 90.760us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
uart_stress_all_with_rand_reset 41.220s 5172.433us 1 1 100.00