Simulation Results: ac_range_check

 
26/11/2025 16:02:05 sha: 2b9f4df json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 82.95 %
  • code
  • 93.19 %
  • assert
  • 97.63 %
  • func
  • 58.02 %
  • block
  • 99.21 %
  • line
  • 99.94 %
  • branch
  • 98.35 %
  • toggle
  • 81.27 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
100.00%
unmapped
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
ac_range_check_smoke 1 1 100.00
ac_range_check_smoke 27.000s 1130.299us 1 1 100.00
ac_range_check_smoke_racl 1 1 100.00
ac_range_check_smoke_racl 31.000s 970.458us 1 1 100.00
csr_hw_reset 1 1 100.00
ac_range_check_csr_hw_reset 2.000s 40.074us 1 1 100.00
csr_rw 1 1 100.00
ac_range_check_csr_rw 3.000s 149.363us 1 1 100.00
csr_bit_bash 1 1 100.00
ac_range_check_csr_bit_bash 35.000s 2607.736us 1 1 100.00
csr_aliasing 1 1 100.00
ac_range_check_csr_aliasing 20.000s 2387.301us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
ac_range_check_csr_mem_rw_with_rand_reset 2.000s 34.578us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
ac_range_check_csr_rw 3.000s 149.363us 1 1 100.00
ac_range_check_csr_aliasing 20.000s 2387.301us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
ac_range_check_lock_range 1 1 100.00
ac_range_check_lock_range 3.000s 33.240us 1 1 100.00
ac_range_bypass_enable 1 1 100.00
ac_range_check_bypass 22.000s 469.841us 1 1 100.00
stress_all 1 1 100.00
ac_range_check_stress_all 110.000s 23587.235us 1 1 100.00
alert_test 1 1 100.00
ac_range_check_alert_test 2.000s 30.393us 1 1 100.00
intr_test 1 1 100.00
ac_range_check_intr_test 2.000s 47.193us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
ac_range_check_tl_errors 2.000s 75.535us 1 1 100.00
tl_d_illegal_access 1 1 100.00
ac_range_check_tl_errors 2.000s 75.535us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
ac_range_check_csr_hw_reset 2.000s 40.074us 1 1 100.00
ac_range_check_csr_rw 3.000s 149.363us 1 1 100.00
ac_range_check_csr_aliasing 20.000s 2387.301us 1 1 100.00
ac_range_check_same_csr_outstanding 5.000s 528.894us 1 1 100.00
tl_d_partial_access 4 4 100.00
ac_range_check_csr_hw_reset 2.000s 40.074us 1 1 100.00
ac_range_check_csr_rw 3.000s 149.363us 1 1 100.00
ac_range_check_csr_aliasing 20.000s 2387.301us 1 1 100.00
ac_range_check_same_csr_outstanding 5.000s 528.894us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
shadow_reg_update_error 1 1 100.00
ac_range_check_shadow_reg_errors 15.000s 3372.194us 1 1 100.00
shadow_reg_read_clear_staged_value 1 1 100.00
ac_range_check_shadow_reg_errors 15.000s 3372.194us 1 1 100.00
shadow_reg_storage_error 1 1 100.00
ac_range_check_shadow_reg_errors 15.000s 3372.194us 1 1 100.00
shadowed_reset_glitch 1 1 100.00
ac_range_check_shadow_reg_errors 15.000s 3372.194us 1 1 100.00
shadow_reg_update_error_with_csr_rw 1 1 100.00
ac_range_check_shadow_reg_errors_with_csr_rw 61.000s 1394.138us 1 1 100.00
tl_intg_err 2 2 100.00
ac_range_check_sec_cm 1.000s 45.597us 1 1 100.00
ac_range_check_tl_intg_err 10.000s 8028.754us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
ac_range_check_stress_all_with_rand_reset 228.000s 444.488us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
Unmapped 1 1 100.00
ac_range_check_smoke_high_threshold 24.000s 4481.505us 1 1 100.00