| chip_sw_spi_device_flash_mode |
0 |
1 |
0.00 |
|
chip_sw_uart_tx_rx_bootstrap |
45.190s |
0.000us |
0 |
1 |
0.00
|
| chip_sw_spi_device_pass_through |
1 |
1 |
100.00 |
|
chip_sw_spi_device_pass_through |
1616.730s |
2831.662us |
1 |
1 |
100.00
|
| chip_sw_spi_device_pass_through_collision |
0 |
1 |
0.00 |
|
chip_sw_spi_device_pass_through_collision |
238.620s |
185.664us |
0 |
1 |
0.00
|
| chip_sw_spi_device_tpm |
0 |
1 |
0.00 |
|
chip_sw_spi_device_tpm |
9.765s |
0.000us |
0 |
1 |
0.00
|
| chip_sw_spi_host_tx_rx |
0 |
1 |
0.00 |
|
chip_sw_spi_host_tx_rx |
10.515s |
0.000us |
0 |
1 |
0.00
|
| chip_sw_i2c_host_tx_rx |
0 |
1 |
0.00 |
|
chip_sw_i2c_host_tx_rx |
10.053s |
0.000us |
0 |
1 |
0.00
|
| chip_sw_i2c_device_tx_rx |
0 |
1 |
0.00 |
|
chip_sw_i2c_device_tx_rx |
10.110s |
0.000us |
0 |
1 |
0.00
|
| chip_pin_mux |
0 |
1 |
0.00 |
|
chip_padctrl_attributes |
2.770s |
0.000us |
0 |
1 |
0.00
|
| chip_padctrl_attributes |
0 |
1 |
0.00 |
|
chip_padctrl_attributes |
2.770s |
0.000us |
0 |
1 |
0.00
|
| chip_sw_sleep_pin_wake |
0 |
1 |
0.00 |
|
chip_sw_sleep_pin_wake |
123.245s |
0.000us |
0 |
1 |
0.00
|
| chip_sw_sleep_pin_retention |
0 |
1 |
0.00 |
|
chip_sw_sleep_pin_retention |
80.182s |
0.000us |
0 |
1 |
0.00
|
| chip_sw_data_integrity |
0 |
1 |
0.00 |
|
chip_sw_data_integrity_escalation |
145.323s |
0.000us |
0 |
1 |
0.00
|
| chip_sw_instruction_integrity |
0 |
1 |
0.00 |
|
chip_sw_data_integrity_escalation |
145.323s |
0.000us |
0 |
1 |
0.00
|
| chip_jtag_csr_rw |
0 |
1 |
0.00 |
|
chip_jtag_csr_rw |
109.120s |
117.042us |
0 |
1 |
0.00
|
| chip_jtag_mem_access |
0 |
1 |
0.00 |
|
chip_jtag_mem_access |
104.570s |
117.025us |
0 |
1 |
0.00
|
| chip_rv_dm_ndm_reset_req |
1 |
1 |
100.00 |
|
chip_rv_dm_ndm_reset_req |
260.800s |
272.883us |
1 |
1 |
100.00
|
| chip_sw_rv_dm_ndm_reset_req_when_cpu_halted |
0 |
1 |
0.00 |
|
chip_sw_rv_dm_ndm_reset_req_when_cpu_halted |
11.908s |
0.000us |
0 |
1 |
0.00
|
| chip_rv_dm_access_after_wakeup |
0 |
1 |
0.00 |
|
chip_sw_rv_dm_access_after_wakeup |
9.619s |
0.000us |
0 |
1 |
0.00
|
| chip_rv_dm_lc_disabled |
0 |
1 |
0.00 |
|
chip_rv_dm_lc_disabled |
80.950s |
128.379us |
0 |
1 |
0.00
|
| chip_sw_timer |
1 |
1 |
100.00 |
|
chip_sw_rv_timer_irq |
248.780s |
248.788us |
1 |
1 |
100.00
|
| chip_sw_aon_timer_wakeup_irq |
0 |
1 |
0.00 |
|
chip_sw_aon_timer_irq |
475.350s |
583.570us |
0 |
1 |
0.00
|
| chip_sw_aon_timer_wdog_bark_irq |
0 |
1 |
0.00 |
|
chip_sw_aon_timer_irq |
475.350s |
583.570us |
0 |
1 |
0.00
|
| chip_sw_aon_timer_wdog_lc_escalate |
1 |
1 |
100.00 |
|
chip_sw_aon_timer_wdog_lc_escalate |
362.540s |
348.682us |
1 |
1 |
100.00
|
| chip_sw_aon_timer_wdog_bite_reset |
0 |
1 |
0.00 |
|
chip_sw_aon_timer_wdog_bite_reset |
212.960s |
164.321us |
0 |
1 |
0.00
|
| chip_sw_aon_timer_sleep_wdog_bite_reset |
0 |
1 |
0.00 |
|
chip_sw_aon_timer_wdog_bite_reset |
212.960s |
164.321us |
0 |
1 |
0.00
|
| chip_sw_aon_timer_sleep_wdog_sleep_pause |
1 |
1 |
100.00 |
|
chip_sw_aon_timer_sleep_wdog_sleep_pause |
293.630s |
2271.494us |
1 |
1 |
100.00
|
| chip_sw_plic_sw_irq |
1 |
1 |
100.00 |
|
chip_sw_plic_sw_irq |
158.050s |
145.509us |
1 |
1 |
100.00
|
| chip_sw_clkmgr_idle_trans |
4 |
4 |
100.00 |
|
chip_sw_otbn_randomness |
267.210s |
225.719us |
1 |
1 |
100.00
|
|
chip_sw_aes_idle |
161.540s |
147.300us |
1 |
1 |
100.00
|
|
chip_sw_hmac_enc_idle |
173.810s |
161.540us |
1 |
1 |
100.00
|
|
chip_sw_kmac_idle |
164.890s |
144.983us |
1 |
1 |
100.00
|
| chip_sw_clkmgr_off_trans |
0 |
4 |
0.00 |
|
chip_sw_clkmgr_off_aes_trans |
162.850s |
165.664us |
0 |
1 |
0.00
|
|
chip_sw_clkmgr_off_hmac_trans |
175.500s |
165.632us |
0 |
1 |
0.00
|
|
chip_sw_clkmgr_off_kmac_trans |
156.950s |
165.632us |
0 |
1 |
0.00
|
|
chip_sw_clkmgr_off_otbn_trans |
177.310s |
165.648us |
0 |
1 |
0.00
|
| chip_sw_clkmgr_jitter |
1 |
7 |
14.29 |
|
chip_sw_otbn_ecdsa_op_irq_jitter_en |
38.550s |
10.240us |
0 |
1 |
0.00
|
|
chip_sw_aes_enc_jitter_en |
41.040s |
10.360us |
0 |
1 |
0.00
|
|
chip_sw_hmac_enc_jitter_en |
37.650s |
10.100us |
0 |
1 |
0.00
|
|
chip_sw_keymgr_dpe_key_derivation_jitter_en |
37.770s |
10.280us |
0 |
1 |
0.00
|
|
chip_sw_kmac_mode_kmac_jitter_en |
36.450s |
10.120us |
0 |
1 |
0.00
|
|
chip_sw_sram_ctrl_scrambled_access_jitter_en |
9.644s |
0.000us |
0 |
1 |
0.00
|
|
chip_sw_clkmgr_jitter |
156.650s |
141.872us |
1 |
1 |
100.00
|
| chip_sw_clkmgr_extended_range |
1 |
8 |
12.50 |
|
chip_sw_clkmgr_jitter_reduced_freq |
332.570s |
1779.439us |
1 |
1 |
100.00
|
|
chip_sw_otbn_ecdsa_op_irq_jitter_en_reduced_freq |
37.860s |
10.380us |
0 |
1 |
0.00
|
|
chip_sw_aes_enc_jitter_en_reduced_freq |
43.240s |
10.280us |
0 |
1 |
0.00
|
|
chip_sw_hmac_enc_jitter_en_reduced_freq |
38.460s |
10.320us |
0 |
1 |
0.00
|
|
chip_sw_keymgr_dpe_key_derivation_jitter_en_reduced_freq |
37.300s |
10.300us |
0 |
1 |
0.00
|
|
chip_sw_kmac_mode_kmac_jitter_en_reduced_freq |
37.560s |
10.180us |
0 |
1 |
0.00
|
|
chip_sw_sram_ctrl_scrambled_access_jitter_en_reduced_freq |
36.260s |
10.400us |
0 |
1 |
0.00
|
|
chip_sw_csrng_edn_concurrency_reduced_freq |
37.710s |
10.200us |
0 |
1 |
0.00
|
| chip_sw_clkmgr_deep_sleep_frequency |
0 |
1 |
0.00 |
|
chip_sw_ast_clk_outputs |
10.617s |
0.000us |
0 |
1 |
0.00
|
| chip_sw_clkmgr_sleep_frequency |
0 |
1 |
0.00 |
|
chip_sw_clkmgr_sleep_frequency |
10.002s |
0.000us |
0 |
1 |
0.00
|
| chip_sw_clkmgr_reset_frequency |
0 |
1 |
0.00 |
|
chip_sw_clkmgr_reset_frequency |
13.441s |
0.000us |
0 |
1 |
0.00
|
| chip_sw_clkmgr_escalation_reset |
0 |
1 |
0.00 |
|
chip_sw_all_escalation_resets |
813.910s |
905.449us |
0 |
1 |
0.00
|
| chip_sw_pwrmgr_external_full_reset |
1 |
1 |
100.00 |
|
chip_sw_pwrmgr_full_aon_reset |
350.410s |
500.873us |
1 |
1 |
100.00
|
| chip_sw_pwrmgr_sleep_all_reset_reqs |
0 |
1 |
0.00 |
|
chip_sw_aon_timer_wdog_bite_reset |
212.960s |
164.321us |
0 |
1 |
0.00
|
| chip_sw_pwrmgr_wdog_reset |
0 |
1 |
0.00 |
|
chip_sw_pwrmgr_wdog_reset |
16.240s |
0.000us |
0 |
1 |
0.00
|
| chip_sw_pwrmgr_aon_power_glitch_reset |
1 |
1 |
100.00 |
|
chip_sw_pwrmgr_full_aon_reset |
350.410s |
500.873us |
1 |
1 |
100.00
|
| chip_sw_pwrmgr_main_power_glitch_reset |
0 |
1 |
0.00 |
|
chip_sw_pwrmgr_main_power_glitch_reset |
11.828s |
0.000us |
0 |
1 |
0.00
|
| chip_sw_pwrmgr_random_sleep_power_glitch_reset |
0 |
1 |
0.00 |
|
chip_sw_pwrmgr_random_sleep_power_glitch_reset |
10.077s |
0.000us |
0 |
1 |
0.00
|
| chip_sw_pwrmgr_deep_sleep_power_glitch_reset |
0 |
1 |
0.00 |
|
chip_sw_pwrmgr_deep_sleep_power_glitch_reset |
10.967s |
0.000us |
0 |
1 |
0.00
|
| chip_sw_pwrmgr_sleep_power_glitch_reset |
0 |
1 |
0.00 |
|
chip_sw_pwrmgr_sleep_power_glitch_reset |
10.613s |
0.000us |
0 |
1 |
0.00
|
| chip_sw_pwrmgr_sleep_disabled |
0 |
1 |
0.00 |
|
chip_sw_pwrmgr_sleep_disabled |
15.833s |
0.000us |
0 |
1 |
0.00
|
| chip_sw_pwrmgr_escalation_reset |
0 |
1 |
0.00 |
|
chip_sw_all_escalation_resets |
813.910s |
905.449us |
0 |
1 |
0.00
|
| chip_sw_rstmgr_sys_reset_info |
1 |
1 |
100.00 |
|
chip_rv_dm_ndm_reset_req |
260.800s |
272.883us |
1 |
1 |
100.00
|
| chip_sw_rstmgr_cpu_info |
0 |
1 |
0.00 |
|
chip_sw_rstmgr_cpu_info |
353.440s |
375.120us |
0 |
1 |
0.00
|
| chip_sw_rstmgr_sw_req_reset |
1 |
1 |
100.00 |
|
chip_sw_rstmgr_sw_req |
286.760s |
267.436us |
1 |
1 |
100.00
|
| chip_sw_rstmgr_alert_info |
0 |
1 |
0.00 |
|
chip_sw_rstmgr_alert_info |
313.920s |
290.246us |
0 |
1 |
0.00
|
| chip_sw_rstmgr_sw_rst |
1 |
1 |
100.00 |
|
chip_sw_rstmgr_sw_rst |
184.310s |
144.150us |
1 |
1 |
100.00
|
| chip_sw_rstmgr_escalation_reset |
0 |
1 |
0.00 |
|
chip_sw_all_escalation_resets |
813.910s |
905.449us |
0 |
1 |
0.00
|
| chip_sw_alert_handler_alerts |
0 |
1 |
0.00 |
|
chip_sw_alert_test |
10.483s |
0.000us |
0 |
1 |
0.00
|
| chip_sw_alert_handler_escalations |
0 |
1 |
0.00 |
|
chip_sw_alert_handler_escalation |
12.184s |
0.000us |
0 |
1 |
0.00
|
| chip_sw_all_escalation_resets |
0 |
1 |
0.00 |
|
chip_sw_all_escalation_resets |
813.910s |
905.449us |
0 |
1 |
0.00
|
| chip_sw_alert_handler_entropy |
0 |
1 |
0.00 |
|
chip_sw_alert_handler_entropy |
12.667s |
0.000us |
0 |
1 |
0.00
|
| chip_sw_alert_handler_crashdump |
0 |
1 |
0.00 |
|
chip_sw_rstmgr_alert_info |
313.920s |
290.246us |
0 |
1 |
0.00
|
| chip_sw_alert_handler_ping_timeout |
1 |
1 |
100.00 |
|
chip_sw_alert_handler_ping_timeout |
388.860s |
419.278us |
1 |
1 |
100.00
|
| chip_sw_alert_handler_lpg_sleep_mode_alerts |
0 |
1 |
0.00 |
|
chip_sw_alert_handler_lpg_sleep_mode_alerts |
10.390s |
0.000us |
0 |
1 |
0.00
|
| chip_sw_alert_handler_lpg_sleep_mode_pings |
0 |
1 |
0.00 |
|
chip_sw_alert_handler_lpg_sleep_mode_pings |
11.054s |
0.000us |
0 |
1 |
0.00
|
| chip_sw_alert_handler_lpg_clock_off |
0 |
1 |
0.00 |
|
chip_sw_alert_handler_lpg_clkoff |
8.965s |
0.000us |
0 |
1 |
0.00
|
| chip_sw_alert_handler_lpg_reset_toggle |
0 |
1 |
0.00 |
|
chip_sw_alert_handler_lpg_reset_toggle |
11.981s |
0.000us |
0 |
1 |
0.00
|
| chip_sw_alert_handler_reverse_ping_in_deep_sleep |
0 |
1 |
0.00 |
|
chip_sw_alert_handler_reverse_ping_in_deep_sleep |
11.656s |
0.000us |
0 |
1 |
0.00
|
| chip_sw_lc_ctrl_alert_handler_escalation |
0 |
1 |
0.00 |
|
chip_sw_alert_handler_escalation |
12.184s |
0.000us |
0 |
1 |
0.00
|
| chip_sw_lc_ctrl_jtag_access |
0 |
1 |
0.00 |
|
chip_sw_lc_ctrl_transition |
11.242s |
0.000us |
0 |
1 |
0.00
|
| chip_sw_lc_ctrl_otp_hw_cfg |
0 |
1 |
0.00 |
|
chip_sw_lc_ctrl_otp_hw_cfg |
12.471s |
0.000us |
0 |
1 |
0.00
|
| chip_sw_lc_ctrl_init |
0 |
1 |
0.00 |
|
chip_sw_lc_ctrl_transition |
11.242s |
0.000us |
0 |
1 |
0.00
|
| chip_sw_lc_ctrl_transitions |
0 |
1 |
0.00 |
|
chip_sw_lc_ctrl_transition |
11.242s |
0.000us |
0 |
1 |
0.00
|
| chip_sw_lc_ctrl_kmac_req |
0 |
1 |
0.00 |
|
chip_sw_lc_ctrl_transition |
11.242s |
0.000us |
0 |
1 |
0.00
|
| chip_sw_lc_ctrl_key_div |
0 |
1 |
0.00 |
|
chip_sw_keymgr_dpe_key_derivation_prod |
271.720s |
267.687us |
0 |
1 |
0.00
|
| chip_sw_lc_ctrl_broadcast |
2 |
10 |
20.00 |
|
chip_prim_tl_access |
494.090s |
730.574us |
1 |
1 |
100.00
|
|
chip_rv_dm_lc_disabled |
80.950s |
128.379us |
0 |
1 |
0.00
|
|
chip_sw_otp_ctrl_lc_signals_test_unlocked0 |
13.093s |
0.000us |
0 |
1 |
0.00
|
|
chip_sw_otp_ctrl_lc_signals_dev |
11.482s |
0.000us |
0 |
1 |
0.00
|
|
chip_sw_otp_ctrl_lc_signals_prod |
10.976s |
0.000us |
0 |
1 |
0.00
|
|
chip_sw_otp_ctrl_lc_signals_rma |
10.412s |
0.000us |
0 |
1 |
0.00
|
|
chip_sw_lc_ctrl_transition |
11.242s |
0.000us |
0 |
1 |
0.00
|
|
chip_sw_keymgr_dpe_key_derivation |
266.610s |
267.792us |
0 |
1 |
0.00
|
|
chip_sw_rom_ctrl_integrity_check |
751.660s |
1266.518us |
1 |
1 |
100.00
|
|
chip_sw_sram_ctrl_execution_main |
11.561s |
0.000us |
0 |
1 |
0.00
|
| chip_sw_aes_enc |
1 |
2 |
50.00 |
|
chip_sw_aes_enc |
169.970s |
157.103us |
1 |
1 |
100.00
|
|
chip_sw_aes_enc_jitter_en |
41.040s |
10.360us |
0 |
1 |
0.00
|
| chip_sw_aes_entropy |
1 |
1 |
100.00 |
|
chip_sw_aes_entropy |
156.100s |
145.878us |
1 |
1 |
100.00
|
| chip_sw_aes_idle |
1 |
1 |
100.00 |
|
chip_sw_aes_idle |
161.540s |
147.300us |
1 |
1 |
100.00
|
| chip_sw_hmac_enc |
1 |
2 |
50.00 |
|
chip_sw_hmac_enc |
180.480s |
156.403us |
1 |
1 |
100.00
|
|
chip_sw_hmac_enc_jitter_en |
37.650s |
10.100us |
0 |
1 |
0.00
|
| chip_sw_hmac_idle |
1 |
1 |
100.00 |
|
chip_sw_hmac_enc_idle |
173.810s |
161.540us |
1 |
1 |
100.00
|
| chip_sw_kmac_enc |
2 |
3 |
66.67 |
|
chip_sw_kmac_mode_cshake |
160.880s |
148.973us |
1 |
1 |
100.00
|
|
chip_sw_kmac_mode_kmac |
216.860s |
172.102us |
1 |
1 |
100.00
|
|
chip_sw_kmac_mode_kmac_jitter_en |
36.450s |
10.120us |
0 |
1 |
0.00
|
| chip_sw_kmac_app_keymgr |
0 |
1 |
0.00 |
|
chip_sw_keymgr_dpe_key_derivation |
266.610s |
267.792us |
0 |
1 |
0.00
|
| chip_sw_kmac_app_lc |
0 |
1 |
0.00 |
|
chip_sw_lc_ctrl_transition |
11.242s |
0.000us |
0 |
1 |
0.00
|
| chip_sw_kmac_app_rom |
0 |
1 |
0.00 |
|
chip_sw_kmac_app_rom |
38.070s |
10.320us |
0 |
1 |
0.00
|
| chip_sw_kmac_entropy |
1 |
1 |
100.00 |
|
chip_sw_kmac_entropy |
225.690s |
178.804us |
1 |
1 |
100.00
|
| chip_sw_kmac_idle |
1 |
1 |
100.00 |
|
chip_sw_kmac_idle |
164.890s |
144.983us |
1 |
1 |
100.00
|
| chip_sw_entropy_src_csrng |
1 |
1 |
100.00 |
|
chip_sw_entropy_src_csrng |
375.390s |
261.601us |
1 |
1 |
100.00
|
| chip_sw_csrng_edn_cmd |
1 |
1 |
100.00 |
|
chip_sw_entropy_src_csrng |
375.390s |
261.601us |
1 |
1 |
100.00
|
| chip_sw_csrng_fuse_en_sw_app_read |
0 |
1 |
0.00 |
|
chip_sw_csrng_fuse_en_sw_app_read_test |
10.826s |
0.000us |
0 |
1 |
0.00
|
| chip_sw_csrng_known_answer_tests |
1 |
1 |
100.00 |
|
chip_sw_csrng_kat_test |
191.050s |
156.819us |
1 |
1 |
100.00
|
| chip_sw_edn_entropy_reqs |
1 |
1 |
100.00 |
|
chip_sw_csrng_edn_concurrency |
2208.540s |
2009.614us |
1 |
1 |
100.00
|
| chip_sw_keymgr_dpe_key_derivation |
0 |
2 |
0.00 |
|
chip_sw_keymgr_dpe_key_derivation |
266.610s |
267.792us |
0 |
1 |
0.00
|
|
chip_sw_keymgr_dpe_key_derivation_jitter_en |
37.770s |
10.280us |
0 |
1 |
0.00
|
| chip_sw_otbn_op |
1 |
2 |
50.00 |
|
chip_sw_otbn_ecdsa_op_irq |
2286.150s |
1463.103us |
1 |
1 |
100.00
|
|
chip_sw_otbn_ecdsa_op_irq_jitter_en |
38.550s |
10.240us |
0 |
1 |
0.00
|
| chip_sw_otbn_rnd_entropy |
1 |
1 |
100.00 |
|
chip_sw_otbn_randomness |
267.210s |
225.719us |
1 |
1 |
100.00
|
| chip_sw_otbn_urnd_entropy |
1 |
1 |
100.00 |
|
chip_sw_otbn_randomness |
267.210s |
225.719us |
1 |
1 |
100.00
|
| chip_sw_otbn_idle |
1 |
1 |
100.00 |
|
chip_sw_otbn_randomness |
267.210s |
225.719us |
1 |
1 |
100.00
|
| chip_sw_otbn_mem_scramble |
1 |
1 |
100.00 |
|
chip_sw_otbn_mem_scramble |
344.620s |
264.963us |
1 |
1 |
100.00
|
| chip_sw_rom_access |
1 |
1 |
100.00 |
|
chip_sw_rom_ctrl_integrity_check |
751.660s |
1266.518us |
1 |
1 |
100.00
|
| chip_sw_rom_ctrl_integrity_check |
1 |
1 |
100.00 |
|
chip_sw_rom_ctrl_integrity_check |
751.660s |
1266.518us |
1 |
1 |
100.00
|
| chip_sw_sram_scrambled_access |
1 |
2 |
50.00 |
|
chip_sw_sram_ctrl_scrambled_access |
323.200s |
314.267us |
1 |
1 |
100.00
|
|
chip_sw_sram_ctrl_scrambled_access_jitter_en |
9.644s |
0.000us |
0 |
1 |
0.00
|
| chip_sw_sram_execution |
0 |
1 |
0.00 |
|
chip_sw_sram_ctrl_execution_main |
11.561s |
0.000us |
0 |
1 |
0.00
|
| chip_sw_sram_lc_escalation |
0 |
2 |
0.00 |
|
chip_sw_all_escalation_resets |
813.910s |
905.449us |
0 |
1 |
0.00
|
|
chip_sw_data_integrity_escalation |
145.323s |
0.000us |
0 |
1 |
0.00
|
| chip_otp_ctrl_init |
0 |
1 |
0.00 |
|
chip_sw_lc_ctrl_transition |
11.242s |
0.000us |
0 |
1 |
0.00
|
| chip_sw_otp_ctrl_keys |
3 |
4 |
75.00 |
|
chip_sw_otbn_mem_scramble |
344.620s |
264.963us |
1 |
1 |
100.00
|
|
chip_sw_keymgr_dpe_key_derivation |
266.610s |
267.792us |
0 |
1 |
0.00
|
|
chip_sw_sram_ctrl_scrambled_access |
323.200s |
314.267us |
1 |
1 |
100.00
|
|
chip_sw_rv_core_ibex_icache_invalidate |
158.690s |
153.783us |
1 |
1 |
100.00
|
| chip_sw_otp_ctrl_entropy |
3 |
4 |
75.00 |
|
chip_sw_otbn_mem_scramble |
344.620s |
264.963us |
1 |
1 |
100.00
|
|
chip_sw_keymgr_dpe_key_derivation |
266.610s |
267.792us |
0 |
1 |
0.00
|
|
chip_sw_sram_ctrl_scrambled_access |
323.200s |
314.267us |
1 |
1 |
100.00
|
|
chip_sw_rv_core_ibex_icache_invalidate |
158.690s |
153.783us |
1 |
1 |
100.00
|
| chip_sw_otp_ctrl_program |
0 |
1 |
0.00 |
|
chip_sw_lc_ctrl_transition |
11.242s |
0.000us |
0 |
1 |
0.00
|
| chip_sw_otp_ctrl_program_error |
0 |
1 |
0.00 |
|
chip_sw_lc_ctrl_program_error |
9.865s |
0.000us |
0 |
1 |
0.00
|
| chip_sw_otp_ctrl_hw_cfg |
0 |
1 |
0.00 |
|
chip_sw_lc_ctrl_otp_hw_cfg |
12.471s |
0.000us |
0 |
1 |
0.00
|
| chip_sw_otp_ctrl_lc_signals |
1 |
6 |
16.67 |
|
chip_prim_tl_access |
494.090s |
730.574us |
1 |
1 |
100.00
|
|
chip_sw_otp_ctrl_lc_signals_test_unlocked0 |
13.093s |
0.000us |
0 |
1 |
0.00
|
|
chip_sw_otp_ctrl_lc_signals_dev |
11.482s |
0.000us |
0 |
1 |
0.00
|
|
chip_sw_otp_ctrl_lc_signals_prod |
10.976s |
0.000us |
0 |
1 |
0.00
|
|
chip_sw_otp_ctrl_lc_signals_rma |
10.412s |
0.000us |
0 |
1 |
0.00
|
|
chip_sw_lc_ctrl_transition |
11.242s |
0.000us |
0 |
1 |
0.00
|
| chip_sw_otp_prim_tl_access |
1 |
1 |
100.00 |
|
chip_prim_tl_access |
494.090s |
730.574us |
1 |
1 |
100.00
|
| chip_sw_otp_ctrl_nvm_cnt |
0 |
1 |
0.00 |
|
chip_sw_otp_ctrl_nvm_cnt |
11.801s |
0.000us |
0 |
1 |
0.00
|
| chip_sw_otp_ctrl_sw_parts |
0 |
1 |
0.00 |
|
chip_sw_otp_ctrl_sw_parts |
11.018s |
0.000us |
0 |
1 |
0.00
|
| chip_sw_ast_clk_outputs |
0 |
1 |
0.00 |
|
chip_sw_ast_clk_outputs |
10.617s |
0.000us |
0 |
1 |
0.00
|
| chip_sw_ast_sys_clk_jitter |
1 |
7 |
14.29 |
|
chip_sw_otbn_ecdsa_op_irq_jitter_en |
38.550s |
10.240us |
0 |
1 |
0.00
|
|
chip_sw_aes_enc_jitter_en |
41.040s |
10.360us |
0 |
1 |
0.00
|
|
chip_sw_hmac_enc_jitter_en |
37.650s |
10.100us |
0 |
1 |
0.00
|
|
chip_sw_keymgr_dpe_key_derivation_jitter_en |
37.770s |
10.280us |
0 |
1 |
0.00
|
|
chip_sw_kmac_mode_kmac_jitter_en |
36.450s |
10.120us |
0 |
1 |
0.00
|
|
chip_sw_sram_ctrl_scrambled_access_jitter_en |
9.644s |
0.000us |
0 |
1 |
0.00
|
|
chip_sw_clkmgr_jitter |
156.650s |
141.872us |
1 |
1 |
100.00
|
| chip_sw_soc_proxy_external_reset_requests |
0 |
1 |
0.00 |
|
chip_sw_soc_proxy_smoketest |
157.550s |
143.504us |
0 |
1 |
0.00
|
| chip_sw_soc_proxy_external_irqs |
0 |
1 |
0.00 |
|
chip_sw_soc_proxy_smoketest |
157.550s |
143.504us |
0 |
1 |
0.00
|
| chip_sw_soc_proxy_external_wakeup_requests |
0 |
1 |
0.00 |
|
chip_sw_soc_proxy_external_wakeup |
147.240s |
138.792us |
0 |
1 |
0.00
|
| chip_sw_soc_proxy_gpios |
0 |
1 |
0.00 |
|
chip_sw_soc_proxy_gpios |
158.080s |
136.470us |
0 |
1 |
0.00
|
| chip_sw_nmi_irq |
0 |
1 |
0.00 |
|
chip_sw_rv_core_ibex_nmi_irq |
335.860s |
251.587us |
0 |
1 |
0.00
|
| chip_sw_rv_core_ibex_rnd |
1 |
1 |
100.00 |
|
chip_sw_rv_core_ibex_rnd |
191.710s |
160.548us |
1 |
1 |
100.00
|
| chip_sw_rv_core_ibex_address_translation |
1 |
1 |
100.00 |
|
chip_sw_rv_core_ibex_address_translation |
176.990s |
164.794us |
1 |
1 |
100.00
|
| chip_sw_rv_core_ibex_icache_scrambled_access |
1 |
1 |
100.00 |
|
chip_sw_rv_core_ibex_icache_invalidate |
158.690s |
153.783us |
1 |
1 |
100.00
|
| chip_sw_rv_core_ibex_fault_dump |
0 |
1 |
0.00 |
|
chip_sw_rstmgr_cpu_info |
353.440s |
375.120us |
0 |
1 |
0.00
|
| chip_sw_rv_core_ibex_double_fault |
0 |
1 |
0.00 |
|
chip_sw_rstmgr_cpu_info |
353.440s |
375.120us |
0 |
1 |
0.00
|
| chip_sw_smoketest |
14 |
14 |
100.00 |
|
chip_sw_aes_smoketest |
143.900s |
157.123us |
1 |
1 |
100.00
|
|
chip_sw_aon_timer_smoketest |
149.240s |
163.236us |
1 |
1 |
100.00
|
|
chip_sw_clkmgr_smoketest |
130.980s |
142.927us |
1 |
1 |
100.00
|
|
chip_sw_csrng_smoketest |
129.980s |
144.804us |
1 |
1 |
100.00
|
|
chip_sw_gpio_smoketest |
147.370s |
165.794us |
1 |
1 |
100.00
|
|
chip_sw_hmac_smoketest |
162.610s |
181.991us |
1 |
1 |
100.00
|
|
chip_sw_kmac_smoketest |
152.760s |
171.094us |
1 |
1 |
100.00
|
|
chip_sw_otbn_smoketest |
177.950s |
193.073us |
1 |
1 |
100.00
|
|
chip_sw_otp_ctrl_smoketest |
122.180s |
146.915us |
1 |
1 |
100.00
|
|
chip_sw_rv_plic_smoketest |
130.420s |
145.047us |
1 |
1 |
100.00
|
|
chip_sw_rv_timer_smoketest |
192.590s |
248.771us |
1 |
1 |
100.00
|
|
chip_sw_rstmgr_smoketest |
125.930s |
141.637us |
1 |
1 |
100.00
|
|
chip_sw_sram_ctrl_smoketest |
130.140s |
145.547us |
1 |
1 |
100.00
|
|
chip_sw_uart_smoketest |
144.890s |
155.769us |
1 |
1 |
100.00
|
| chip_sw_rom_functests |
0 |
1 |
0.00 |
|
rom_keymgr_functest |
10.316s |
0.000us |
0 |
1 |
0.00
|
| chip_sw_signed |
0 |
1 |
0.00 |
|
chip_sw_uart_smoketest_signed |
9.475s |
0.000us |
0 |
1 |
0.00
|
| chip_sw_boot |
0 |
1 |
0.00 |
|
chip_sw_uart_tx_rx_bootstrap |
45.190s |
0.000us |
0 |
1 |
0.00
|
| chip_sw_secure_boot |
0 |
1 |
0.00 |
|
base_rom_e2e_smoke |
10.127s |
0.000us |
0 |
1 |
0.00
|
| chip_lc_scrap |
4 |
4 |
100.00 |
|
chip_sw_lc_ctrl_rma_to_scrap |
183.030s |
196.951us |
1 |
1 |
100.00
|
|
chip_sw_lc_ctrl_raw_to_scrap |
186.890s |
220.233us |
1 |
1 |
100.00
|
|
chip_sw_lc_ctrl_test_locked0_to_scrap |
185.390s |
227.568us |
1 |
1 |
100.00
|
|
chip_sw_lc_ctrl_rand_to_scrap |
206.550s |
218.053us |
1 |
1 |
100.00
|
| chip_lc_test_locked |
0 |
2 |
0.00 |
|
chip_rv_dm_lc_disabled |
80.950s |
128.379us |
0 |
1 |
0.00
|
|
chip_sw_lc_walkthrough_testunlocks |
13.755s |
0.000us |
0 |
1 |
0.00
|
| chip_sw_lc_walkthrough |
0 |
5 |
0.00 |
|
chip_sw_lc_walkthrough_dev |
11.848s |
0.000us |
0 |
1 |
0.00
|
|
chip_sw_lc_walkthrough_prod |
10.551s |
0.000us |
0 |
1 |
0.00
|
|
chip_sw_lc_walkthrough_prodend |
10.048s |
0.000us |
0 |
1 |
0.00
|
|
chip_sw_lc_walkthrough_rma |
10.912s |
0.000us |
0 |
1 |
0.00
|
|
chip_sw_lc_walkthrough_testunlocks |
13.755s |
0.000us |
0 |
1 |
0.00
|
| chip_sw_lc_ctrl_volatile_raw_unlock |
2 |
3 |
66.67 |
|
chip_sw_lc_ctrl_volatile_raw_unlock |
456.290s |
559.948us |
1 |
1 |
100.00
|
|
chip_sw_lc_ctrl_volatile_raw_unlock_ext_clk_48mhz |
438.340s |
540.161us |
1 |
1 |
100.00
|
|
rom_volatile_raw_unlock |
10.263s |
0.000us |
0 |
1 |
0.00
|
| chip_sw_rom_raw_unlock |
0 |
1 |
0.00 |
|
rom_raw_unlock |
10.006s |
0.000us |
0 |
1 |
0.00
|
| chip_sw_exit_test_unlocked_bootstrap |
0 |
1 |
0.00 |
|
chip_sw_exit_test_unlocked_bootstrap |
27.556s |
0.000us |
0 |
1 |
0.00
|
| chip_sw_inject_scramble_seed |
0 |
1 |
0.00 |
|
chip_sw_inject_scramble_seed |
38.368s |
0.000us |
0 |
1 |
0.00
|
| tl_d_oob_addr_access |
0 |
1 |
0.00 |
|
chip_tl_errors |
110.780s |
117.963us |
0 |
1 |
0.00
|
| tl_d_illegal_access |
0 |
1 |
0.00 |
|
chip_tl_errors |
110.780s |
117.963us |
0 |
1 |
0.00
|
| tl_d_outstanding_access |
0 |
2 |
0.00 |
|
chip_csr_aliasing |
8.800s |
0.000us |
0 |
1 |
0.00
|
|
chip_same_csr_outstanding |
10.820s |
0.000us |
0 |
1 |
0.00
|
| tl_d_partial_access |
0 |
2 |
0.00 |
|
chip_csr_aliasing |
8.800s |
0.000us |
0 |
1 |
0.00
|
|
chip_same_csr_outstanding |
10.820s |
0.000us |
0 |
1 |
0.00
|
| xbar_base_random_sequence |
1 |
1 |
100.00 |
|
xbar_random |
87.440s |
214.294us |
1 |
1 |
100.00
|
| xbar_random_delay |
6 |
6 |
100.00 |
|
xbar_smoke_zero_delays |
9.140s |
12.773us |
1 |
1 |
100.00
|
|
xbar_smoke_large_delays |
282.310s |
2221.594us |
1 |
1 |
100.00
|
|
xbar_smoke_slow_rsp |
361.390s |
2037.715us |
1 |
1 |
100.00
|
|
xbar_random_zero_delays |
34.380s |
32.940us |
1 |
1 |
100.00
|
|
xbar_random_large_delays |
728.720s |
5741.478us |
1 |
1 |
100.00
|
|
xbar_random_slow_rsp |
2160.190s |
12927.587us |
1 |
1 |
100.00
|
| xbar_unmapped_address |
2 |
2 |
100.00 |
|
xbar_unmapped_addr |
20.700s |
16.389us |
1 |
1 |
100.00
|
|
xbar_error_and_unmapped_addr |
24.470s |
47.509us |
1 |
1 |
100.00
|
| xbar_error_cases |
2 |
2 |
100.00 |
|
xbar_error_random |
64.210s |
67.648us |
1 |
1 |
100.00
|
|
xbar_error_and_unmapped_addr |
24.470s |
47.509us |
1 |
1 |
100.00
|
| xbar_all_access_same_device |
2 |
2 |
100.00 |
|
xbar_access_same_device |
229.920s |
558.376us |
1 |
1 |
100.00
|
|
xbar_access_same_device_slow_rsp |
2750.890s |
16711.698us |
1 |
1 |
100.00
|
| xbar_all_hosts_use_same_source_id |
1 |
1 |
100.00 |
|
xbar_same_source |
26.570s |
59.588us |
1 |
1 |
100.00
|
| xbar_stress_all |
2 |
2 |
100.00 |
|
xbar_stress_all |
171.720s |
144.005us |
1 |
1 |
100.00
|
|
xbar_stress_all_with_error |
1096.650s |
2946.328us |
1 |
1 |
100.00
|
| xbar_stress_with_reset |
2 |
2 |
100.00 |
|
xbar_stress_all_with_rand_reset |
1023.070s |
589.543us |
1 |
1 |
100.00
|
|
xbar_stress_all_with_reset_error |
786.220s |
579.892us |
1 |
1 |
100.00
|
| rom_e2e_smoke |
0 |
1 |
0.00 |
|
rom_e2e_smoke |
9.851s |
0.000us |
0 |
1 |
0.00
|
| rom_e2e_shutdown_output |
0 |
1 |
0.00 |
|
rom_e2e_shutdown_output |
9.465s |
0.000us |
0 |
1 |
0.00
|
| rom_e2e_shutdown_exception_c |
0 |
1 |
0.00 |
|
rom_e2e_shutdown_exception_c |
9.895s |
0.000us |
0 |
1 |
0.00
|
| rom_e2e_boot_policy_valid |
0 |
15 |
0.00 |
|
rom_e2e_boot_policy_valid_a_good_b_good_test_unlocked0 |
9.421s |
0.000us |
0 |
1 |
0.00
|
|
rom_e2e_boot_policy_valid_a_good_b_good_dev |
10.962s |
0.000us |
0 |
1 |
0.00
|
|
rom_e2e_boot_policy_valid_a_good_b_good_prod |
10.207s |
0.000us |
0 |
1 |
0.00
|
|
rom_e2e_boot_policy_valid_a_good_b_good_prod_end |
9.322s |
0.000us |
0 |
1 |
0.00
|
|
rom_e2e_boot_policy_valid_a_good_b_good_rma |
9.754s |
0.000us |
0 |
1 |
0.00
|
|
rom_e2e_boot_policy_valid_a_good_b_bad_test_unlocked0 |
11.203s |
0.000us |
0 |
1 |
0.00
|
|
rom_e2e_boot_policy_valid_a_good_b_bad_dev |
9.702s |
0.000us |
0 |
1 |
0.00
|
|
rom_e2e_boot_policy_valid_a_good_b_bad_prod |
10.902s |
0.000us |
0 |
1 |
0.00
|
|
rom_e2e_boot_policy_valid_a_good_b_bad_prod_end |
9.389s |
0.000us |
0 |
1 |
0.00
|
|
rom_e2e_boot_policy_valid_a_good_b_bad_rma |
9.548s |
0.000us |
0 |
1 |
0.00
|
|
rom_e2e_boot_policy_valid_a_bad_b_good_test_unlocked0 |
52.730s |
0.000us |
0 |
1 |
0.00
|
|
rom_e2e_boot_policy_valid_a_bad_b_good_dev |
75.334s |
0.000us |
0 |
1 |
0.00
|
|
rom_e2e_boot_policy_valid_a_bad_b_good_prod |
68.739s |
0.000us |
0 |
1 |
0.00
|
|
rom_e2e_boot_policy_valid_a_bad_b_good_prod_end |
69.801s |
0.000us |
0 |
1 |
0.00
|
|
rom_e2e_boot_policy_valid_a_bad_b_good_rma |
68.706s |
0.000us |
0 |
1 |
0.00
|
| rom_e2e_sigverify_always |
0 |
15 |
0.00 |
|
rom_e2e_sigverify_always_a_bad_b_bad_test_unlocked0 |
74.263s |
0.000us |
0 |
1 |
0.00
|
|
rom_e2e_sigverify_always_a_bad_b_bad_dev |
70.301s |
0.000us |
0 |
1 |
0.00
|
|
rom_e2e_sigverify_always_a_bad_b_bad_prod |
65.507s |
0.000us |
0 |
1 |
0.00
|
|
rom_e2e_sigverify_always_a_bad_b_bad_prod_end |
72.897s |
0.000us |
0 |
1 |
0.00
|
|
rom_e2e_sigverify_always_a_bad_b_bad_rma |
56.065s |
0.000us |
0 |
1 |
0.00
|
|
rom_e2e_sigverify_always_a_bad_b_nothing_test_unlocked0 |
65.195s |
0.000us |
0 |
1 |
0.00
|
|
rom_e2e_sigverify_always_a_bad_b_nothing_dev |
66.655s |
0.000us |
0 |
1 |
0.00
|
|
rom_e2e_sigverify_always_a_bad_b_nothing_prod |
62.858s |
0.000us |
0 |
1 |
0.00
|
|
rom_e2e_sigverify_always_a_bad_b_nothing_prod_end |
59.844s |
0.000us |
0 |
1 |
0.00
|
|
rom_e2e_sigverify_always_a_bad_b_nothing_rma |
55.508s |
0.000us |
0 |
1 |
0.00
|
|
rom_e2e_sigverify_always_a_nothing_b_bad_test_unlocked0 |
10.408s |
0.000us |
0 |
1 |
0.00
|
|
rom_e2e_sigverify_always_a_nothing_b_bad_dev |
11.974s |
0.000us |
0 |
1 |
0.00
|
|
rom_e2e_sigverify_always_a_nothing_b_bad_prod |
11.847s |
0.000us |
0 |
1 |
0.00
|
|
rom_e2e_sigverify_always_a_nothing_b_bad_prod_end |
11.910s |
0.000us |
0 |
1 |
0.00
|
|
rom_e2e_sigverify_always_a_nothing_b_bad_rma |
12.169s |
0.000us |
0 |
1 |
0.00
|
| rom_e2e_asm_init |
0 |
5 |
0.00 |
|
rom_e2e_asm_init_test_unlocked0 |
13.182s |
0.000us |
0 |
1 |
0.00
|
|
rom_e2e_asm_init_dev |
12.564s |
0.000us |
0 |
1 |
0.00
|
|
rom_e2e_asm_init_prod |
15.444s |
0.000us |
0 |
1 |
0.00
|
|
rom_e2e_asm_init_prod_end |
11.629s |
0.000us |
0 |
1 |
0.00
|
|
rom_e2e_asm_init_rma |
9.572s |
0.000us |
0 |
1 |
0.00
|
| rom_e2e_keymgr_init |
0 |
3 |
0.00 |
|
rom_e2e_keymgr_init_rom_ext_meas |
9.430s |
0.000us |
0 |
1 |
0.00
|
|
rom_e2e_keymgr_init_rom_ext_no_meas |
9.452s |
0.000us |
0 |
1 |
0.00
|
|
rom_e2e_keymgr_init_rom_ext_invalid_meas |
9.940s |
0.000us |
0 |
1 |
0.00
|
| rom_e2e_static_critical |
0 |
1 |
0.00 |
|
rom_e2e_static_critical |
9.483s |
0.000us |
0 |
1 |
0.00
|