Simulation Results: clkmgr

 
26/11/2025 16:02:05 sha: 2b9f4df json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 78.14 %
  • code
  • 69.87 %
  • assert
  • 90.29 %
  • func
  • 74.25 %
  • line
  • 82.45 %
  • branch
  • 87.58 %
  • cond
  • 80.05 %
  • toggle
  • 99.25 %
  • FSM
  • 0.00 %
Validation stages
V1
62.50%
V2
57.89%
V2S
70.59%
V3
0.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
clkmgr_smoke 0.910s 22.772us 1 1 100.00
csr_hw_reset 1 1 100.00
clkmgr_csr_hw_reset 0.780s 24.646us 1 1 100.00
csr_rw 1 1 100.00
clkmgr_csr_rw 0.770s 24.327us 1 1 100.00
csr_bit_bash 0 1 0.00
clkmgr_csr_bit_bash 1.080s 67.843us 0 1 0.00
csr_aliasing 0 1 0.00
clkmgr_csr_aliasing 0.700s 5.411us 0 1 0.00
csr_mem_rw_with_rand_reset 1 1 100.00
clkmgr_csr_mem_rw_with_rand_reset 0.890s 22.810us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 1 2 50.00
clkmgr_csr_rw 0.770s 24.327us 1 1 100.00
clkmgr_csr_aliasing 0.700s 5.411us 0 1 0.00
Testpoint Test Max Runtime Sim Time Pass Total %
peri_enables 1 1 100.00
clkmgr_peri 0.820s 25.447us 1 1 100.00
trans_enables 1 1 100.00
clkmgr_trans 0.770s 22.249us 1 1 100.00
clk_status 1 1 100.00
clkmgr_clk_status 1.040s 43.642us 1 1 100.00
jitter 1 1 100.00
clkmgr_smoke 0.910s 22.772us 1 1 100.00
frequency 0 1 0.00
clkmgr_frequency 0.700s 13.525us 0 1 0.00
frequency_timeout 0 1 0.00
clkmgr_frequency_timeout 0.650s 6.026us 0 1 0.00
frequency_overflow 0 1 0.00
clkmgr_frequency 0.700s 13.525us 0 1 0.00
stress_all 0 1 0.00
clkmgr_stress_all 1.070s 54.744us 0 1 0.00
alert_test 1 1 100.00
clkmgr_alert_test 0.750s 16.788us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
clkmgr_tl_errors 5.390s 564.489us 1 1 100.00
tl_d_illegal_access 1 1 100.00
clkmgr_tl_errors 5.390s 564.489us 1 1 100.00
tl_d_outstanding_access 2 4 50.00
clkmgr_csr_hw_reset 0.780s 24.646us 1 1 100.00
clkmgr_csr_rw 0.770s 24.327us 1 1 100.00
clkmgr_csr_aliasing 0.700s 5.411us 0 1 0.00
clkmgr_same_csr_outstanding 0.770s 7.579us 0 1 0.00
tl_d_partial_access 2 4 50.00
clkmgr_csr_hw_reset 0.780s 24.646us 1 1 100.00
clkmgr_csr_rw 0.770s 24.327us 1 1 100.00
clkmgr_csr_aliasing 0.700s 5.411us 0 1 0.00
clkmgr_same_csr_outstanding 0.770s 7.579us 0 1 0.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 1 2 50.00
clkmgr_sec_cm 2.740s 255.630us 1 1 100.00
clkmgr_tl_intg_err 0.610s 2.743us 0 1 0.00
shadow_reg_update_error 1 1 100.00
clkmgr_shadow_reg_errors 1.230s 61.719us 1 1 100.00
shadow_reg_read_clear_staged_value 1 1 100.00
clkmgr_shadow_reg_errors 1.230s 61.719us 1 1 100.00
shadow_reg_storage_error 1 1 100.00
clkmgr_shadow_reg_errors 1.230s 61.719us 1 1 100.00
shadowed_reset_glitch 1 1 100.00
clkmgr_shadow_reg_errors 1.230s 61.719us 1 1 100.00
shadow_reg_update_error_with_csr_rw 0 1 0.00
clkmgr_shadow_reg_errors_with_csr_rw 0.630s 5.559us 0 1 0.00
sec_cm_bus_integrity 0 1 0.00
clkmgr_tl_intg_err 0.610s 2.743us 0 1 0.00
sec_cm_meas_clk_bkgn_chk 0 1 0.00
clkmgr_frequency 0.700s 13.525us 0 1 0.00
sec_cm_timeout_clk_bkgn_chk 0 1 0.00
clkmgr_frequency_timeout 0.650s 6.026us 0 1 0.00
sec_cm_meas_config_shadow 1 1 100.00
clkmgr_shadow_reg_errors 1.230s 61.719us 1 1 100.00
sec_cm_idle_intersig_mubi 1 1 100.00
clkmgr_idle_intersig_mubi 0.980s 42.246us 1 1 100.00
sec_cm_jitter_config_mubi 1 1 100.00
clkmgr_csr_rw 0.770s 24.327us 1 1 100.00
sec_cm_idle_ctr_redun 1 1 100.00
clkmgr_sec_cm 2.740s 255.630us 1 1 100.00
sec_cm_meas_config_regwen 1 1 100.00
clkmgr_csr_rw 0.770s 24.327us 1 1 100.00
sec_cm_clk_ctrl_config_regwen 1 1 100.00
clkmgr_csr_rw 0.770s 24.327us 1 1 100.00
prim_count_check 1 1 100.00
clkmgr_sec_cm 2.740s 255.630us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
regwen 0 1 0.00
clkmgr_regwen 0.660s 6.726us 0 1 0.00
stress_all_with_rand_reset 0 1 0.00
clkmgr_stress_all_with_rand_reset 2.290s 131.194us 0 1 0.00