Simulation Results: csrng

 
26/11/2025 16:02:05 sha: 2b9f4df json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 85.82 %
  • code
  • 91.89 %
  • assert
  • 92.15 %
  • func
  • 73.41 %
  • block
  • 96.83 %
  • line
  • 97.75 %
  • branch
  • 92.32 %
  • toggle
  • 91.77 %
  • FSM
  • 85.71 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
csrng_smoke 3.000s 45.768us 1 1 100.00
csr_hw_reset 1 1 100.00
csrng_csr_hw_reset 3.000s 40.441us 1 1 100.00
csr_rw 1 1 100.00
csrng_csr_rw 3.000s 15.188us 1 1 100.00
csr_bit_bash 1 1 100.00
csrng_csr_bit_bash 8.000s 217.620us 1 1 100.00
csr_aliasing 1 1 100.00
csrng_csr_aliasing 3.000s 72.790us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
csrng_csr_mem_rw_with_rand_reset 2.000s 32.838us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
csrng_csr_rw 3.000s 15.188us 1 1 100.00
csrng_csr_aliasing 3.000s 72.790us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
interrupts 1 1 100.00
csrng_intr 4.000s 51.882us 1 1 100.00
alerts 1 1 100.00
csrng_alert 10.000s 367.362us 1 1 100.00
err 1 1 100.00
csrng_err 2.000s 21.974us 1 1 100.00
cmds 1 1 100.00
csrng_cmds 120.000s 7644.510us 1 1 100.00
life cycle 1 1 100.00
csrng_cmds 120.000s 7644.510us 1 1 100.00
stress_all 1 1 100.00
csrng_stress_all 63.000s 1575.023us 1 1 100.00
intr_test 1 1 100.00
csrng_intr_test 3.000s 39.348us 1 1 100.00
alert_test 1 1 100.00
csrng_alert_test 5.000s 104.188us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
csrng_tl_errors 4.000s 43.682us 1 1 100.00
tl_d_illegal_access 1 1 100.00
csrng_tl_errors 4.000s 43.682us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
csrng_csr_hw_reset 3.000s 40.441us 1 1 100.00
csrng_csr_rw 3.000s 15.188us 1 1 100.00
csrng_csr_aliasing 3.000s 72.790us 1 1 100.00
csrng_same_csr_outstanding 4.000s 95.839us 1 1 100.00
tl_d_partial_access 4 4 100.00
csrng_csr_hw_reset 3.000s 40.441us 1 1 100.00
csrng_csr_rw 3.000s 15.188us 1 1 100.00
csrng_csr_aliasing 3.000s 72.790us 1 1 100.00
csrng_same_csr_outstanding 4.000s 95.839us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
csrng_sec_cm 5.000s 89.929us 1 1 100.00
csrng_tl_intg_err 11.000s 554.156us 1 1 100.00
sec_cm_config_regwen 2 2 100.00
csrng_regwen 2.000s 18.589us 1 1 100.00
csrng_csr_rw 3.000s 15.188us 1 1 100.00
sec_cm_config_mubi 1 1 100.00
csrng_alert 10.000s 367.362us 1 1 100.00
sec_cm_intersig_mubi 1 1 100.00
csrng_stress_all 63.000s 1575.023us 1 1 100.00
sec_cm_main_sm_fsm_sparse 3 3 100.00
csrng_intr 4.000s 51.882us 1 1 100.00
csrng_err 2.000s 21.974us 1 1 100.00
csrng_sec_cm 5.000s 89.929us 1 1 100.00
sec_cm_updrsp_fsm_sparse 3 3 100.00
csrng_intr 4.000s 51.882us 1 1 100.00
csrng_err 2.000s 21.974us 1 1 100.00
csrng_sec_cm 5.000s 89.929us 1 1 100.00
sec_cm_update_fsm_sparse 3 3 100.00
csrng_intr 4.000s 51.882us 1 1 100.00
csrng_err 2.000s 21.974us 1 1 100.00
csrng_sec_cm 5.000s 89.929us 1 1 100.00
sec_cm_blk_enc_fsm_sparse 3 3 100.00
csrng_intr 4.000s 51.882us 1 1 100.00
csrng_err 2.000s 21.974us 1 1 100.00
csrng_sec_cm 5.000s 89.929us 1 1 100.00
sec_cm_outblk_fsm_sparse 3 3 100.00
csrng_intr 4.000s 51.882us 1 1 100.00
csrng_err 2.000s 21.974us 1 1 100.00
csrng_sec_cm 5.000s 89.929us 1 1 100.00
sec_cm_gen_cmd_ctr_redun 3 3 100.00
csrng_intr 4.000s 51.882us 1 1 100.00
csrng_err 2.000s 21.974us 1 1 100.00
csrng_sec_cm 5.000s 89.929us 1 1 100.00
sec_cm_drbg_upd_ctr_redun 3 3 100.00
csrng_intr 4.000s 51.882us 1 1 100.00
csrng_err 2.000s 21.974us 1 1 100.00
csrng_sec_cm 5.000s 89.929us 1 1 100.00
sec_cm_drbg_gen_ctr_redun 3 3 100.00
csrng_intr 4.000s 51.882us 1 1 100.00
csrng_err 2.000s 21.974us 1 1 100.00
csrng_sec_cm 5.000s 89.929us 1 1 100.00
sec_cm_ctrl_mubi 1 1 100.00
csrng_alert 10.000s 367.362us 1 1 100.00
sec_cm_main_sm_ctr_local_esc 2 2 100.00
csrng_intr 4.000s 51.882us 1 1 100.00
csrng_err 2.000s 21.974us 1 1 100.00
sec_cm_constants_lc_gated 1 1 100.00
csrng_stress_all 63.000s 1575.023us 1 1 100.00
sec_cm_sw_genbits_bus_consistency 1 1 100.00
csrng_alert 10.000s 367.362us 1 1 100.00
sec_cm_tile_link_bus_integrity 1 1 100.00
csrng_tl_intg_err 11.000s 554.156us 1 1 100.00
sec_cm_aes_cipher_fsm_sparse 3 3 100.00
csrng_intr 4.000s 51.882us 1 1 100.00
csrng_err 2.000s 21.974us 1 1 100.00
csrng_sec_cm 5.000s 89.929us 1 1 100.00
sec_cm_aes_cipher_fsm_redun 2 2 100.00
csrng_intr 4.000s 51.882us 1 1 100.00
csrng_err 2.000s 21.974us 1 1 100.00
sec_cm_aes_cipher_ctrl_sparse 2 2 100.00
csrng_intr 4.000s 51.882us 1 1 100.00
csrng_err 2.000s 21.974us 1 1 100.00
sec_cm_aes_cipher_fsm_local_esc 2 2 100.00
csrng_intr 4.000s 51.882us 1 1 100.00
csrng_err 2.000s 21.974us 1 1 100.00
sec_cm_aes_cipher_ctr_redun 3 3 100.00
csrng_intr 4.000s 51.882us 1 1 100.00
csrng_err 2.000s 21.974us 1 1 100.00
csrng_sec_cm 5.000s 89.929us 1 1 100.00
sec_cm_aes_cipher_data_reg_local_esc 2 2 100.00
csrng_intr 4.000s 51.882us 1 1 100.00
csrng_err 2.000s 21.974us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
csrng_stress_all_with_rand_reset 156.000s 3900.939us 1 1 100.00