Simulation Results: dma

 
26/11/2025 16:02:05 sha: 2b9f4df json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 83.24 %
  • code
  • 91.82 %
  • assert
  • 95.97 %
  • func
  • 61.93 %
  • block
  • 97.34 %
  • line
  • 96.85 %
  • branch
  • 95.76 %
  • toggle
  • 83.12 %
  • FSM
  • 91.55 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
unmapped
66.67%
Testpoint Test Max Runtime Sim Time Pass Total %
dma_memory_smoke 1 1 100.00
dma_memory_smoke 5.000s 350.841us 1 1 100.00
dma_handshake_smoke 1 1 100.00
dma_handshake_smoke 5.000s 986.373us 1 1 100.00
dma_generic_smoke 1 1 100.00
dma_generic_smoke 5.000s 388.537us 1 1 100.00
csr_hw_reset 1 1 100.00
dma_csr_hw_reset 1.000s 17.291us 1 1 100.00
csr_rw 1 1 100.00
dma_csr_rw 2.000s 111.951us 1 1 100.00
csr_bit_bash 1 1 100.00
dma_csr_bit_bash 7.000s 691.347us 1 1 100.00
csr_aliasing 1 1 100.00
dma_csr_aliasing 6.000s 156.290us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
dma_csr_mem_rw_with_rand_reset 2.000s 342.041us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
dma_csr_rw 2.000s 111.951us 1 1 100.00
dma_csr_aliasing 6.000s 156.290us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
dma_memory_region_lock 1 1 100.00
dma_memory_region_lock 94.000s 68593.117us 1 1 100.00
dma_memory_tl_error 1 1 100.00
dma_memory_stress 980.000s 206255.406us 1 1 100.00
dma_handshake_tl_error 1 1 100.00
dma_handshake_stress 457.000s 219198.832us 1 1 100.00
dma_handshake_stress 1 1 100.00
dma_handshake_stress 457.000s 219198.832us 1 1 100.00
dma_memory_stress 1 1 100.00
dma_memory_stress 980.000s 206255.406us 1 1 100.00
dma_generic_stress 1 1 100.00
dma_generic_stress 157.000s 30274.303us 1 1 100.00
dma_handshake_mem_buffer_overflow 1 1 100.00
dma_handshake_stress 457.000s 219198.832us 1 1 100.00
dma_abort 1 1 100.00
dma_abort 8.000s 642.670us 1 1 100.00
dma_stress_all 1 1 100.00
dma_stress_all 216.000s 79883.744us 1 1 100.00
alert_test 1 1 100.00
dma_alert_test 2.000s 37.073us 1 1 100.00
intr_test 1 1 100.00
dma_intr_test 1.000s 25.108us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
dma_tl_errors 2.000s 333.033us 1 1 100.00
tl_d_illegal_access 1 1 100.00
dma_tl_errors 2.000s 333.033us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
dma_csr_hw_reset 1.000s 17.291us 1 1 100.00
dma_csr_rw 2.000s 111.951us 1 1 100.00
dma_csr_aliasing 6.000s 156.290us 1 1 100.00
dma_same_csr_outstanding 2.000s 322.228us 1 1 100.00
tl_d_partial_access 4 4 100.00
dma_csr_hw_reset 1.000s 17.291us 1 1 100.00
dma_csr_rw 2.000s 111.951us 1 1 100.00
dma_csr_aliasing 6.000s 156.290us 1 1 100.00
dma_same_csr_outstanding 2.000s 322.228us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
dma_illegal_addr_range 3 3 100.00
dma_mem_enabled 18.000s 346.982us 1 1 100.00
dma_generic_stress 157.000s 30274.303us 1 1 100.00
dma_handshake_stress 457.000s 219198.832us 1 1 100.00
dma_config_lock 1 1 100.00
dma_config_lock 7.000s 1393.983us 1 1 100.00
tl_intg_err 2 2 100.00
dma_tl_intg_err 3.000s 101.171us 1 1 100.00
dma_sec_cm 2.000s 12.412us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
Unmapped 2 3 66.67
dma_short_transfer 65.000s 18061.710us 1 1 100.00
dma_longer_transfer 11.000s 981.657us 1 1 100.00
dma_stress_all_with_rand_reset 3.000s 2097.285us 0 1 0.00