Simulation Results: edn

 
26/11/2025 16:02:05 sha: 2b9f4df json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 84.18 %
  • code
  • 82.18 %
  • assert
  • 94.22 %
  • func
  • 76.15 %
  • line
  • 97.45 %
  • branch
  • 91.20 %
  • cond
  • 86.90 %
  • toggle
  • 85.34 %
  • FSM
  • 50.00 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
edn_smoke 0.850s 48.737us 1 1 100.00
csr_hw_reset 1 1 100.00
edn_csr_hw_reset 0.770s 51.807us 1 1 100.00
csr_rw 1 1 100.00
edn_csr_rw 0.800s 14.884us 1 1 100.00
csr_bit_bash 1 1 100.00
edn_csr_bit_bash 3.340s 343.084us 1 1 100.00
csr_aliasing 1 1 100.00
edn_csr_aliasing 0.860s 35.250us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
edn_csr_mem_rw_with_rand_reset 1.080s 36.818us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
edn_csr_rw 0.800s 14.884us 1 1 100.00
edn_csr_aliasing 0.860s 35.250us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
firmware 1 1 100.00
edn_genbits 1.230s 47.944us 1 1 100.00
csrng_commands 1 1 100.00
edn_genbits 1.230s 47.944us 1 1 100.00
genbits 1 1 100.00
edn_genbits 1.230s 47.944us 1 1 100.00
interrupts 1 1 100.00
edn_intr 0.880s 21.138us 1 1 100.00
alerts 1 1 100.00
edn_alert 1.090s 31.902us 1 1 100.00
errs 1 1 100.00
edn_err 0.800s 21.383us 1 1 100.00
disable 2 2 100.00
edn_disable 0.730s 17.725us 1 1 100.00
edn_disable_auto_req_mode 0.930s 61.638us 1 1 100.00
stress_all 1 1 100.00
edn_stress_all 2.920s 360.054us 1 1 100.00
intr_test 1 1 100.00
edn_intr_test 0.780s 70.910us 1 1 100.00
alert_test 1 1 100.00
edn_alert_test 0.950s 25.185us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
edn_tl_errors 1.150s 40.480us 1 1 100.00
tl_d_illegal_access 1 1 100.00
edn_tl_errors 1.150s 40.480us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
edn_csr_hw_reset 0.770s 51.807us 1 1 100.00
edn_csr_rw 0.800s 14.884us 1 1 100.00
edn_csr_aliasing 0.860s 35.250us 1 1 100.00
edn_same_csr_outstanding 0.970s 102.869us 1 1 100.00
tl_d_partial_access 4 4 100.00
edn_csr_hw_reset 0.770s 51.807us 1 1 100.00
edn_csr_rw 0.800s 14.884us 1 1 100.00
edn_csr_aliasing 0.860s 35.250us 1 1 100.00
edn_same_csr_outstanding 0.970s 102.869us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
edn_sec_cm 2.980s 313.198us 1 1 100.00
edn_tl_intg_err 1.210s 84.994us 1 1 100.00
sec_cm_config_regwen 1 1 100.00
edn_regwen 0.810s 64.947us 1 1 100.00
sec_cm_config_mubi 1 1 100.00
edn_alert 1.090s 31.902us 1 1 100.00
sec_cm_main_sm_fsm_sparse 1 1 100.00
edn_sec_cm 2.980s 313.198us 1 1 100.00
sec_cm_ack_sm_fsm_sparse 1 1 100.00
edn_sec_cm 2.980s 313.198us 1 1 100.00
sec_cm_fifo_ctr_redun 1 1 100.00
edn_sec_cm 2.980s 313.198us 1 1 100.00
sec_cm_ctr_redun 1 1 100.00
edn_sec_cm 2.980s 313.198us 1 1 100.00
sec_cm_main_sm_ctr_local_esc 2 2 100.00
edn_alert 1.090s 31.902us 1 1 100.00
edn_sec_cm 2.980s 313.198us 1 1 100.00
sec_cm_cs_rdata_bus_consistency 1 1 100.00
edn_alert 1.090s 31.902us 1 1 100.00
sec_cm_tile_link_bus_integrity 1 1 100.00
edn_tl_intg_err 1.210s 84.994us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
edn_stress_all_with_rand_reset 24.390s 5274.488us 1 1 100.00