Simulation Results: hmac

 
26/11/2025 16:02:05 sha: 2b9f4df json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 79.51 %
  • code
  • 98.03 %
  • assert
  • 96.42 %
  • func
  • 44.07 %
  • line
  • 99.79 %
  • branch
  • 99.67 %
  • cond
  • 96.57 %
  • toggle
  • 100.00 %
  • FSM
  • 94.12 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
100.00%
unmapped
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
hmac_smoke 3.020s 295.797us 1 1 100.00
csr_hw_reset 1 1 100.00
hmac_csr_hw_reset 0.860s 20.386us 1 1 100.00
csr_rw 1 1 100.00
hmac_csr_rw 0.860s 28.648us 1 1 100.00
csr_bit_bash 1 1 100.00
hmac_csr_bit_bash 6.620s 480.501us 1 1 100.00
csr_aliasing 1 1 100.00
hmac_csr_aliasing 2.120s 67.663us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
hmac_csr_mem_rw_with_rand_reset 0.820s 16.199us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
hmac_csr_rw 0.860s 28.648us 1 1 100.00
hmac_csr_aliasing 2.120s 67.663us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
long_msg 1 1 100.00
hmac_long_msg 14.760s 7391.204us 1 1 100.00
back_pressure 1 1 100.00
hmac_back_pressure 6.470s 340.939us 1 1 100.00
test_vectors 6 6 100.00
hmac_test_sha256_vectors 154.050s 5228.231us 1 1 100.00
hmac_test_sha384_vectors 18.010s 232.871us 1 1 100.00
hmac_test_sha512_vectors 414.180s 26572.185us 1 1 100.00
hmac_test_hmac256_vectors 5.410s 187.134us 1 1 100.00
hmac_test_hmac384_vectors 10.070s 3038.129us 1 1 100.00
hmac_test_hmac512_vectors 8.490s 301.770us 1 1 100.00
burst_wr 1 1 100.00
hmac_burst_wr 13.350s 389.997us 1 1 100.00
datapath_stress 1 1 100.00
hmac_datapath_stress 0.840s 43.161us 1 1 100.00
error 1 1 100.00
hmac_error 56.650s 5166.190us 1 1 100.00
wipe_secret 1 1 100.00
hmac_wipe_secret 24.100s 3093.195us 1 1 100.00
save_and_restore 6 6 100.00
hmac_smoke 3.020s 295.797us 1 1 100.00
hmac_long_msg 14.760s 7391.204us 1 1 100.00
hmac_back_pressure 6.470s 340.939us 1 1 100.00
hmac_datapath_stress 0.840s 43.161us 1 1 100.00
hmac_burst_wr 13.350s 389.997us 1 1 100.00
hmac_stress_all 32.220s 5343.439us 1 1 100.00
fifo_empty_status_interrupt 11 11 100.00
hmac_smoke 3.020s 295.797us 1 1 100.00
hmac_long_msg 14.760s 7391.204us 1 1 100.00
hmac_back_pressure 6.470s 340.939us 1 1 100.00
hmac_datapath_stress 0.840s 43.161us 1 1 100.00
hmac_wipe_secret 24.100s 3093.195us 1 1 100.00
hmac_test_sha256_vectors 154.050s 5228.231us 1 1 100.00
hmac_test_sha384_vectors 18.010s 232.871us 1 1 100.00
hmac_test_sha512_vectors 414.180s 26572.185us 1 1 100.00
hmac_test_hmac256_vectors 5.410s 187.134us 1 1 100.00
hmac_test_hmac384_vectors 10.070s 3038.129us 1 1 100.00
hmac_test_hmac512_vectors 8.490s 301.770us 1 1 100.00
wide_digest_configurable_key_length 14 14 100.00
hmac_smoke 3.020s 295.797us 1 1 100.00
hmac_long_msg 14.760s 7391.204us 1 1 100.00
hmac_back_pressure 6.470s 340.939us 1 1 100.00
hmac_datapath_stress 0.840s 43.161us 1 1 100.00
hmac_burst_wr 13.350s 389.997us 1 1 100.00
hmac_error 56.650s 5166.190us 1 1 100.00
hmac_wipe_secret 24.100s 3093.195us 1 1 100.00
hmac_test_sha256_vectors 154.050s 5228.231us 1 1 100.00
hmac_test_sha384_vectors 18.010s 232.871us 1 1 100.00
hmac_test_sha512_vectors 414.180s 26572.185us 1 1 100.00
hmac_test_hmac256_vectors 5.410s 187.134us 1 1 100.00
hmac_test_hmac384_vectors 10.070s 3038.129us 1 1 100.00
hmac_test_hmac512_vectors 8.490s 301.770us 1 1 100.00
hmac_stress_all 32.220s 5343.439us 1 1 100.00
stress_all 1 1 100.00
hmac_stress_all 32.220s 5343.439us 1 1 100.00
alert_test 1 1 100.00
hmac_alert_test 0.630s 44.595us 1 1 100.00
intr_test 1 1 100.00
hmac_intr_test 0.660s 79.731us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
hmac_tl_errors 1.590s 93.044us 1 1 100.00
tl_d_illegal_access 1 1 100.00
hmac_tl_errors 1.590s 93.044us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
hmac_csr_hw_reset 0.860s 20.386us 1 1 100.00
hmac_csr_rw 0.860s 28.648us 1 1 100.00
hmac_csr_aliasing 2.120s 67.663us 1 1 100.00
hmac_same_csr_outstanding 1.410s 235.728us 1 1 100.00
tl_d_partial_access 4 4 100.00
hmac_csr_hw_reset 0.860s 20.386us 1 1 100.00
hmac_csr_rw 0.860s 28.648us 1 1 100.00
hmac_csr_aliasing 2.120s 67.663us 1 1 100.00
hmac_same_csr_outstanding 1.410s 235.728us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
hmac_sec_cm 0.860s 183.528us 1 1 100.00
hmac_tl_intg_err 2.220s 643.998us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
hmac_tl_intg_err 2.220s 643.998us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
write_config_and_secret_key_during_msg_wr 1 1 100.00
hmac_smoke 3.020s 295.797us 1 1 100.00
stress_reset 1 1 100.00
hmac_stress_reset 5.330s 403.020us 1 1 100.00
stress_all_with_rand_reset 1 1 100.00
hmac_stress_all_with_rand_reset 57.530s 5307.572us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
Unmapped 1 1 100.00
hmac_directed 0.700s 16.162us 1 1 100.00