| host_error_intr |
0 |
1 |
0.00 |
|
i2c_host_error_intr |
2.540s |
233.739us |
0 |
1 |
0.00
|
| host_stress_all |
0 |
1 |
0.00 |
|
i2c_host_stress_all |
0.000s |
0.000us |
0 |
1 |
0.00
|
| host_maxperf |
1 |
1 |
100.00 |
|
i2c_host_perf |
17.580s |
7847.236us |
1 |
1 |
100.00
|
| host_override |
1 |
1 |
100.00 |
|
i2c_host_override |
0.710s |
114.211us |
1 |
1 |
100.00
|
| host_fifo_watermark |
1 |
1 |
100.00 |
|
i2c_host_fifo_watermark |
138.340s |
20243.285us |
1 |
1 |
100.00
|
| host_fifo_overflow |
1 |
1 |
100.00 |
|
i2c_host_fifo_overflow |
57.110s |
2801.830us |
1 |
1 |
100.00
|
| host_fifo_reset |
3 |
3 |
100.00 |
|
i2c_host_fifo_reset_fmt |
0.880s |
140.287us |
1 |
1 |
100.00
|
|
i2c_host_fifo_fmt_empty |
3.130s |
260.801us |
1 |
1 |
100.00
|
|
i2c_host_fifo_reset_rx |
5.760s |
194.523us |
1 |
1 |
100.00
|
| host_fifo_full |
1 |
1 |
100.00 |
|
i2c_host_fifo_full |
69.560s |
32619.944us |
1 |
1 |
100.00
|
| host_timeout |
1 |
1 |
100.00 |
|
i2c_host_stretch_timeout |
19.020s |
615.190us |
1 |
1 |
100.00
|
| i2c_host_mode_toggle |
0 |
1 |
0.00 |
|
i2c_host_mode_toggle |
1.100s |
59.648us |
0 |
1 |
0.00
|
| target_glitch |
0 |
1 |
0.00 |
|
i2c_target_glitch |
1.980s |
2334.614us |
0 |
1 |
0.00
|
| target_stress_all |
1 |
1 |
100.00 |
|
i2c_target_stress_all |
58.720s |
24692.548us |
1 |
1 |
100.00
|
| target_maxperf |
1 |
1 |
100.00 |
|
i2c_target_perf |
3.530s |
1485.345us |
1 |
1 |
100.00
|
| target_fifo_empty |
2 |
2 |
100.00 |
|
i2c_target_stress_rd |
12.350s |
1989.820us |
1 |
1 |
100.00
|
|
i2c_target_intr_smoke |
2.960s |
704.750us |
1 |
1 |
100.00
|
| target_fifo_reset |
2 |
2 |
100.00 |
|
i2c_target_fifo_reset_acq |
1.200s |
153.344us |
1 |
1 |
100.00
|
|
i2c_target_fifo_reset_tx |
1.020s |
615.183us |
1 |
1 |
100.00
|
| target_fifo_full |
3 |
3 |
100.00 |
|
i2c_target_stress_wr |
90.460s |
52841.161us |
1 |
1 |
100.00
|
|
i2c_target_stress_rd |
12.350s |
1989.820us |
1 |
1 |
100.00
|
|
i2c_target_intr_stress_wr |
9.260s |
4281.569us |
1 |
1 |
100.00
|
| target_timeout |
1 |
1 |
100.00 |
|
i2c_target_timeout |
4.680s |
5965.031us |
1 |
1 |
100.00
|
| target_clock_stretch |
1 |
1 |
100.00 |
|
i2c_target_stretch |
39.600s |
3943.260us |
1 |
1 |
100.00
|
| bad_address |
1 |
1 |
100.00 |
|
i2c_target_bad_addr |
5.610s |
6637.447us |
1 |
1 |
100.00
|
| target_mode_glitch |
0 |
1 |
0.00 |
|
i2c_target_hrst |
20.130s |
10279.607us |
0 |
1 |
0.00
|
| target_fifo_watermark |
2 |
2 |
100.00 |
|
i2c_target_fifo_watermarks_acq |
2.070s |
1579.493us |
1 |
1 |
100.00
|
|
i2c_target_fifo_watermarks_tx |
1.010s |
73.816us |
1 |
1 |
100.00
|
| host_mode_config_perf |
2 |
2 |
100.00 |
|
i2c_host_perf |
17.580s |
7847.236us |
1 |
1 |
100.00
|
|
i2c_host_perf_precise |
1.090s |
240.923us |
1 |
1 |
100.00
|
| host_mode_clock_stretching |
1 |
1 |
100.00 |
|
i2c_host_stretch_timeout |
19.020s |
615.190us |
1 |
1 |
100.00
|
| target_mode_tx_stretch_ctrl |
1 |
1 |
100.00 |
|
i2c_target_tx_stretch_ctrl |
3.860s |
344.623us |
1 |
1 |
100.00
|
| target_mode_nack_generation |
2 |
3 |
66.67 |
|
i2c_target_nack_acqfull |
2.160s |
1139.137us |
1 |
1 |
100.00
|
|
i2c_target_nack_acqfull_addr |
2.010s |
8268.970us |
1 |
1 |
100.00
|
|
i2c_target_nack_txstretch |
1.110s |
134.476us |
0 |
1 |
0.00
|
| host_mode_halt_on_nak |
1 |
1 |
100.00 |
|
i2c_host_may_nack |
3.540s |
595.704us |
1 |
1 |
100.00
|
| target_mode_smbus_maxlen |
1 |
1 |
100.00 |
|
i2c_target_smbus_maxlen |
1.840s |
2272.824us |
1 |
1 |
100.00
|
| alert_test |
1 |
1 |
100.00 |
|
i2c_alert_test |
0.750s |
16.785us |
1 |
1 |
100.00
|
| intr_test |
1 |
1 |
100.00 |
|
i2c_intr_test |
0.680s |
22.966us |
1 |
1 |
100.00
|
| tl_d_oob_addr_access |
1 |
1 |
100.00 |
|
i2c_tl_errors |
1.660s |
52.926us |
1 |
1 |
100.00
|
| tl_d_illegal_access |
1 |
1 |
100.00 |
|
i2c_tl_errors |
1.660s |
52.926us |
1 |
1 |
100.00
|
| tl_d_outstanding_access |
4 |
4 |
100.00 |
|
i2c_csr_hw_reset |
0.710s |
17.717us |
1 |
1 |
100.00
|
|
i2c_csr_rw |
0.910s |
25.588us |
1 |
1 |
100.00
|
|
i2c_csr_aliasing |
1.520s |
143.983us |
1 |
1 |
100.00
|
|
i2c_same_csr_outstanding |
0.920s |
91.065us |
1 |
1 |
100.00
|
| tl_d_partial_access |
4 |
4 |
100.00 |
|
i2c_csr_hw_reset |
0.710s |
17.717us |
1 |
1 |
100.00
|
|
i2c_csr_rw |
0.910s |
25.588us |
1 |
1 |
100.00
|
|
i2c_csr_aliasing |
1.520s |
143.983us |
1 |
1 |
100.00
|
|
i2c_same_csr_outstanding |
0.920s |
91.065us |
1 |
1 |
100.00
|