Simulation Results: lc_ctrl

 
26/11/2025 16:02:05 sha: 2b9f4df json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 90.20 %
  • code
  • 88.43 %
  • assert
  • 95.85 %
  • func
  • 86.33 %
  • line
  • 97.69 %
  • branch
  • 96.56 %
  • cond
  • 79.84 %
  • toggle
  • 82.34 %
  • FSM
  • 85.71 %
Validation stages
V1
100.00%
V2
85.00%
V2S
64.29%
V3
0.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
lc_ctrl_smoke 2.780s 137.400us 1 1 100.00
csr_hw_reset 1 1 100.00
lc_ctrl_csr_hw_reset 0.860s 44.129us 1 1 100.00
csr_rw 1 1 100.00
lc_ctrl_csr_rw 0.990s 16.757us 1 1 100.00
csr_bit_bash 1 1 100.00
lc_ctrl_csr_bit_bash 1.190s 28.319us 1 1 100.00
csr_aliasing 1 1 100.00
lc_ctrl_csr_aliasing 1.000s 34.497us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
lc_ctrl_csr_mem_rw_with_rand_reset 1.160s 87.664us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
lc_ctrl_csr_rw 0.990s 16.757us 1 1 100.00
lc_ctrl_csr_aliasing 1.000s 34.497us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
state_post_trans 0 1 0.00
lc_ctrl_state_post_trans 1.330s 56.577us 0 1 0.00
regwen_during_op 1 1 100.00
lc_ctrl_regwen_during_op 10.890s 610.675us 1 1 100.00
rand_wr_claim_transition_if 1 1 100.00
lc_ctrl_claim_transition_if 0.770s 14.085us 1 1 100.00
lc_prog_failure 1 1 100.00
lc_ctrl_prog_failure 1.770s 841.264us 1 1 100.00
lc_state_failure 0 1 0.00
lc_ctrl_state_failure 4.670s 39.418us 0 1 0.00
lc_errors 1 1 100.00
lc_ctrl_errors 5.360s 434.447us 1 1 100.00
security_escalation 5 7 71.43
lc_ctrl_state_failure 4.670s 39.418us 0 1 0.00
lc_ctrl_prog_failure 1.770s 841.264us 1 1 100.00
lc_ctrl_errors 5.360s 434.447us 1 1 100.00
lc_ctrl_security_escalation 4.720s 320.732us 1 1 100.00
lc_ctrl_jtag_state_failure 4.560s 229.350us 0 1 0.00
lc_ctrl_jtag_prog_failure 18.100s 4497.275us 1 1 100.00
lc_ctrl_jtag_errors 27.720s 1477.930us 1 1 100.00
jtag_access 12 13 92.31
lc_ctrl_jtag_smoke 5.730s 3998.384us 1 1 100.00
lc_ctrl_jtag_state_post_trans 2.110s 124.691us 0 1 0.00
lc_ctrl_jtag_prog_failure 18.100s 4497.275us 1 1 100.00
lc_ctrl_jtag_errors 27.720s 1477.930us 1 1 100.00
lc_ctrl_jtag_access 8.540s 946.669us 1 1 100.00
lc_ctrl_jtag_regwen_during_op 8.100s 4020.045us 1 1 100.00
lc_ctrl_jtag_csr_hw_reset 1.820s 275.069us 1 1 100.00
lc_ctrl_jtag_csr_rw 2.210s 215.912us 1 1 100.00
lc_ctrl_jtag_csr_bit_bash 11.570s 1376.348us 1 1 100.00
lc_ctrl_jtag_csr_aliasing 4.480s 715.075us 1 1 100.00
lc_ctrl_jtag_same_csr_outstanding 1.180s 71.870us 1 1 100.00
lc_ctrl_jtag_csr_mem_rw_with_rand_reset 1.800s 132.353us 1 1 100.00
lc_ctrl_jtag_alert_test 1.000s 46.876us 1 1 100.00
jtag_priority 1 1 100.00
lc_ctrl_jtag_priority 1.510s 552.391us 1 1 100.00
lc_ctrl_volatile_unlock 1 1 100.00
lc_ctrl_volatile_unlock_smoke 0.760s 13.850us 1 1 100.00
stress_all 0 1 0.00
lc_ctrl_stress_all 174.500s 33609.766us 0 1 0.00
alert_test 1 1 100.00
lc_ctrl_alert_test 1.280s 47.819us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
lc_ctrl_tl_errors 1.510s 120.314us 1 1 100.00
tl_d_illegal_access 1 1 100.00
lc_ctrl_tl_errors 1.510s 120.314us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
lc_ctrl_csr_hw_reset 0.860s 44.129us 1 1 100.00
lc_ctrl_csr_rw 0.990s 16.757us 1 1 100.00
lc_ctrl_csr_aliasing 1.000s 34.497us 1 1 100.00
lc_ctrl_same_csr_outstanding 1.090s 75.643us 1 1 100.00
tl_d_partial_access 4 4 100.00
lc_ctrl_csr_hw_reset 0.860s 44.129us 1 1 100.00
lc_ctrl_csr_rw 0.990s 16.757us 1 1 100.00
lc_ctrl_csr_aliasing 1.000s 34.497us 1 1 100.00
lc_ctrl_same_csr_outstanding 1.090s 75.643us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
lc_ctrl_sec_cm 6.520s 601.273us 1 1 100.00
lc_ctrl_tl_intg_err 2.170s 339.176us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
lc_ctrl_tl_intg_err 2.170s 339.176us 1 1 100.00
sec_cm_transition_config_regwen 1 1 100.00
lc_ctrl_regwen_during_op 10.890s 610.675us 1 1 100.00
sec_cm_manuf_state_sparse 1 2 50.00
lc_ctrl_state_failure 4.670s 39.418us 0 1 0.00
lc_ctrl_sec_cm 6.520s 601.273us 1 1 100.00
sec_cm_transition_ctr_sparse 1 2 50.00
lc_ctrl_state_failure 4.670s 39.418us 0 1 0.00
lc_ctrl_sec_cm 6.520s 601.273us 1 1 100.00
sec_cm_manuf_state_bkgn_chk 1 2 50.00
lc_ctrl_state_failure 4.670s 39.418us 0 1 0.00
lc_ctrl_sec_cm 6.520s 601.273us 1 1 100.00
sec_cm_transition_ctr_bkgn_chk 1 2 50.00
lc_ctrl_state_failure 4.670s 39.418us 0 1 0.00
lc_ctrl_sec_cm 6.520s 601.273us 1 1 100.00
sec_cm_state_config_sparse 1 2 50.00
lc_ctrl_state_failure 4.670s 39.418us 0 1 0.00
lc_ctrl_sec_cm 6.520s 601.273us 1 1 100.00
sec_cm_main_fsm_sparse 1 2 50.00
lc_ctrl_state_failure 4.670s 39.418us 0 1 0.00
lc_ctrl_sec_cm 6.520s 601.273us 1 1 100.00
sec_cm_kmac_fsm_sparse 1 2 50.00
lc_ctrl_state_failure 4.670s 39.418us 0 1 0.00
lc_ctrl_sec_cm 6.520s 601.273us 1 1 100.00
sec_cm_main_fsm_local_esc 1 2 50.00
lc_ctrl_state_failure 4.670s 39.418us 0 1 0.00
lc_ctrl_sec_cm 6.520s 601.273us 1 1 100.00
sec_cm_main_fsm_global_esc 1 1 100.00
lc_ctrl_security_escalation 4.720s 320.732us 1 1 100.00
sec_cm_main_ctrl_flow_consistency 0 2 0.00
lc_ctrl_state_post_trans 1.330s 56.577us 0 1 0.00
lc_ctrl_jtag_state_post_trans 2.110s 124.691us 0 1 0.00
sec_cm_intersig_mubi 1 1 100.00
lc_ctrl_sec_mubi 7.490s 1265.496us 1 1 100.00
sec_cm_token_valid_ctrl_mubi 1 1 100.00
lc_ctrl_sec_mubi 7.490s 1265.496us 1 1 100.00
sec_cm_token_digest 1 1 100.00
lc_ctrl_sec_token_digest 15.180s 1062.290us 1 1 100.00
sec_cm_token_mux_ctrl_redun 1 1 100.00
lc_ctrl_sec_token_mux 6.530s 502.632us 1 1 100.00
sec_cm_token_valid_mux_redun 1 1 100.00
lc_ctrl_sec_token_mux 6.530s 502.632us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 0 1 0.00
lc_ctrl_stress_all_with_rand_reset 10.020s 563.507us 0 1 0.00