Simulation Results: lc_ctrl

 
26/11/2025 16:02:05 sha: 2b9f4df json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 89.31 %
  • code
  • 86.88 %
  • assert
  • 95.99 %
  • func
  • 85.07 %
  • line
  • 97.50 %
  • branch
  • 96.01 %
  • cond
  • 79.39 %
  • toggle
  • 82.41 %
  • FSM
  • 79.07 %
Validation stages
V1
100.00%
V2
85.00%
V2S
64.29%
V3
0.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
lc_ctrl_smoke 2.780s 131.305us 1 1 100.00
csr_hw_reset 1 1 100.00
lc_ctrl_csr_hw_reset 0.730s 16.370us 1 1 100.00
csr_rw 1 1 100.00
lc_ctrl_csr_rw 0.860s 239.404us 1 1 100.00
csr_bit_bash 1 1 100.00
lc_ctrl_csr_bit_bash 1.160s 25.802us 1 1 100.00
csr_aliasing 1 1 100.00
lc_ctrl_csr_aliasing 1.220s 128.294us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
lc_ctrl_csr_mem_rw_with_rand_reset 1.140s 25.579us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
lc_ctrl_csr_rw 0.860s 239.404us 1 1 100.00
lc_ctrl_csr_aliasing 1.220s 128.294us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
state_post_trans 0 1 0.00
lc_ctrl_state_post_trans 3.260s 27.646us 0 1 0.00
regwen_during_op 1 1 100.00
lc_ctrl_regwen_during_op 5.650s 155.983us 1 1 100.00
rand_wr_claim_transition_if 1 1 100.00
lc_ctrl_claim_transition_if 0.810s 23.131us 1 1 100.00
lc_prog_failure 1 1 100.00
lc_ctrl_prog_failure 2.040s 83.432us 1 1 100.00
lc_state_failure 0 1 0.00
lc_ctrl_state_failure 5.250s 80.082us 0 1 0.00
lc_errors 1 1 100.00
lc_ctrl_errors 5.970s 1599.382us 1 1 100.00
security_escalation 5 7 71.43
lc_ctrl_state_failure 5.250s 80.082us 0 1 0.00
lc_ctrl_prog_failure 2.040s 83.432us 1 1 100.00
lc_ctrl_errors 5.970s 1599.382us 1 1 100.00
lc_ctrl_security_escalation 7.000s 504.163us 1 1 100.00
lc_ctrl_jtag_state_failure 2.510s 188.203us 0 1 0.00
lc_ctrl_jtag_prog_failure 2.630s 371.398us 1 1 100.00
lc_ctrl_jtag_errors 26.640s 1496.980us 1 1 100.00
jtag_access 12 13 92.31
lc_ctrl_jtag_smoke 3.770s 417.661us 1 1 100.00
lc_ctrl_jtag_state_post_trans 2.760s 771.644us 0 1 0.00
lc_ctrl_jtag_prog_failure 2.630s 371.398us 1 1 100.00
lc_ctrl_jtag_errors 26.640s 1496.980us 1 1 100.00
lc_ctrl_jtag_access 3.410s 163.269us 1 1 100.00
lc_ctrl_jtag_regwen_during_op 12.170s 7482.549us 1 1 100.00
lc_ctrl_jtag_csr_hw_reset 1.730s 307.438us 1 1 100.00
lc_ctrl_jtag_csr_rw 1.730s 173.896us 1 1 100.00
lc_ctrl_jtag_csr_bit_bash 7.730s 1529.271us 1 1 100.00
lc_ctrl_jtag_csr_aliasing 8.970s 558.107us 1 1 100.00
lc_ctrl_jtag_same_csr_outstanding 1.470s 40.239us 1 1 100.00
lc_ctrl_jtag_csr_mem_rw_with_rand_reset 1.870s 516.447us 1 1 100.00
lc_ctrl_jtag_alert_test 0.980s 42.862us 1 1 100.00
jtag_priority 1 1 100.00
lc_ctrl_jtag_priority 3.500s 473.179us 1 1 100.00
lc_ctrl_volatile_unlock 1 1 100.00
lc_ctrl_volatile_unlock_smoke 0.900s 13.962us 1 1 100.00
stress_all 0 1 0.00
lc_ctrl_stress_all 4.140s 186.044us 0 1 0.00
alert_test 1 1 100.00
lc_ctrl_alert_test 1.420s 28.671us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
lc_ctrl_tl_errors 1.060s 24.062us 1 1 100.00
tl_d_illegal_access 1 1 100.00
lc_ctrl_tl_errors 1.060s 24.062us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
lc_ctrl_csr_hw_reset 0.730s 16.370us 1 1 100.00
lc_ctrl_csr_rw 0.860s 239.404us 1 1 100.00
lc_ctrl_csr_aliasing 1.220s 128.294us 1 1 100.00
lc_ctrl_same_csr_outstanding 1.020s 22.811us 1 1 100.00
tl_d_partial_access 4 4 100.00
lc_ctrl_csr_hw_reset 0.730s 16.370us 1 1 100.00
lc_ctrl_csr_rw 0.860s 239.404us 1 1 100.00
lc_ctrl_csr_aliasing 1.220s 128.294us 1 1 100.00
lc_ctrl_same_csr_outstanding 1.020s 22.811us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
lc_ctrl_sec_cm 7.210s 476.610us 1 1 100.00
lc_ctrl_tl_intg_err 1.280s 60.061us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
lc_ctrl_tl_intg_err 1.280s 60.061us 1 1 100.00
sec_cm_transition_config_regwen 1 1 100.00
lc_ctrl_regwen_during_op 5.650s 155.983us 1 1 100.00
sec_cm_manuf_state_sparse 1 2 50.00
lc_ctrl_state_failure 5.250s 80.082us 0 1 0.00
lc_ctrl_sec_cm 7.210s 476.610us 1 1 100.00
sec_cm_transition_ctr_sparse 1 2 50.00
lc_ctrl_state_failure 5.250s 80.082us 0 1 0.00
lc_ctrl_sec_cm 7.210s 476.610us 1 1 100.00
sec_cm_manuf_state_bkgn_chk 1 2 50.00
lc_ctrl_state_failure 5.250s 80.082us 0 1 0.00
lc_ctrl_sec_cm 7.210s 476.610us 1 1 100.00
sec_cm_transition_ctr_bkgn_chk 1 2 50.00
lc_ctrl_state_failure 5.250s 80.082us 0 1 0.00
lc_ctrl_sec_cm 7.210s 476.610us 1 1 100.00
sec_cm_state_config_sparse 1 2 50.00
lc_ctrl_state_failure 5.250s 80.082us 0 1 0.00
lc_ctrl_sec_cm 7.210s 476.610us 1 1 100.00
sec_cm_main_fsm_sparse 1 2 50.00
lc_ctrl_state_failure 5.250s 80.082us 0 1 0.00
lc_ctrl_sec_cm 7.210s 476.610us 1 1 100.00
sec_cm_kmac_fsm_sparse 1 2 50.00
lc_ctrl_state_failure 5.250s 80.082us 0 1 0.00
lc_ctrl_sec_cm 7.210s 476.610us 1 1 100.00
sec_cm_main_fsm_local_esc 1 2 50.00
lc_ctrl_state_failure 5.250s 80.082us 0 1 0.00
lc_ctrl_sec_cm 7.210s 476.610us 1 1 100.00
sec_cm_main_fsm_global_esc 1 1 100.00
lc_ctrl_security_escalation 7.000s 504.163us 1 1 100.00
sec_cm_main_ctrl_flow_consistency 0 2 0.00
lc_ctrl_state_post_trans 3.260s 27.646us 0 1 0.00
lc_ctrl_jtag_state_post_trans 2.760s 771.644us 0 1 0.00
sec_cm_intersig_mubi 1 1 100.00
lc_ctrl_sec_mubi 7.780s 1141.228us 1 1 100.00
sec_cm_token_valid_ctrl_mubi 1 1 100.00
lc_ctrl_sec_mubi 7.780s 1141.228us 1 1 100.00
sec_cm_token_digest 1 1 100.00
lc_ctrl_sec_token_digest 8.070s 368.763us 1 1 100.00
sec_cm_token_mux_ctrl_redun 1 1 100.00
lc_ctrl_sec_token_mux 5.680s 1096.539us 1 1 100.00
sec_cm_token_valid_mux_redun 1 1 100.00
lc_ctrl_sec_token_mux 5.680s 1096.539us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 0 1 0.00
lc_ctrl_stress_all_with_rand_reset 22.600s 6226.420us 0 1 0.00