| V1 |
|
100.00% |
| V2 |
|
93.75% |
| V2S |
|
100.00% |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| mbx_smoke | 1 | 1 | 100.00 | |||
| mbx_smoke | 28.000s | 2372.105us | 1 | 1 | 100.00 | |
| csr_hw_reset | 1 | 1 | 100.00 | |||
| mbx_csr_hw_reset | 1.000s | 51.559us | 1 | 1 | 100.00 | |
| csr_rw | 1 | 1 | 100.00 | |||
| mbx_csr_rw | 2.000s | 39.090us | 1 | 1 | 100.00 | |
| csr_bit_bash | 1 | 1 | 100.00 | |||
| mbx_csr_bit_bash | 2.000s | 121.533us | 1 | 1 | 100.00 | |
| csr_aliasing | 1 | 1 | 100.00 | |||
| mbx_csr_aliasing | 2.000s | 123.250us | 1 | 1 | 100.00 | |
| csr_mem_rw_with_rand_reset | 1 | 1 | 100.00 | |||
| mbx_csr_mem_rw_with_rand_reset | 1.000s | 62.150us | 1 | 1 | 100.00 | |
| regwen_csr_and_corresponding_lockable_csr | 2 | 2 | 100.00 | |||
| mbx_csr_rw | 2.000s | 39.090us | 1 | 1 | 100.00 | |
| mbx_csr_aliasing | 2.000s | 123.250us | 1 | 1 | 100.00 | |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| mbx_stress | 0 | 1 | 0.00 | |||
| mbx_stress | 6.000s | 273.720us | 0 | 1 | 0.00 | |
| mbx_max_activity | 1 | 1 | 100.00 | |||
| mbx_stress_zero_delays | 28.000s | 3253.348us | 1 | 1 | 100.00 | |
| mbx_imbx_oob | 1 | 1 | 100.00 | |||
| mbx_imbx_oob | 28.000s | 3182.505us | 1 | 1 | 100.00 | |
| mbx_doe_intr_msg | 1 | 1 | 100.00 | |||
| mbx_doe_intr_msg | 9.000s | 674.492us | 1 | 1 | 100.00 | |
| alert_test | 1 | 1 | 100.00 | |||
| mbx_alert_test | 2.000s | 25.731us | 1 | 1 | 100.00 | |
| intr_test | 1 | 1 | 100.00 | |||
| mbx_intr_test | 1.000s | 24.405us | 1 | 1 | 100.00 | |
| tl_d_oob_addr_access | 1 | 1 | 100.00 | |||
| mbx_tl_errors | 4.000s | 425.670us | 1 | 1 | 100.00 | |
| tl_d_illegal_access | 1 | 1 | 100.00 | |||
| mbx_tl_errors | 4.000s | 425.670us | 1 | 1 | 100.00 | |
| tl_d_outstanding_access | 4 | 4 | 100.00 | |||
| mbx_csr_hw_reset | 1.000s | 51.559us | 1 | 1 | 100.00 | |
| mbx_csr_rw | 2.000s | 39.090us | 1 | 1 | 100.00 | |
| mbx_csr_aliasing | 2.000s | 123.250us | 1 | 1 | 100.00 | |
| mbx_same_csr_outstanding | 1.000s | 21.446us | 1 | 1 | 100.00 | |
| tl_d_partial_access | 4 | 4 | 100.00 | |||
| mbx_csr_hw_reset | 1.000s | 51.559us | 1 | 1 | 100.00 | |
| mbx_csr_rw | 2.000s | 39.090us | 1 | 1 | 100.00 | |
| mbx_csr_aliasing | 2.000s | 123.250us | 1 | 1 | 100.00 | |
| mbx_same_csr_outstanding | 1.000s | 21.446us | 1 | 1 | 100.00 | |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| tl_intg_err | 2 | 2 | 100.00 | |||
| mbx_sec_cm | 1.000s | 25.124us | 1 | 1 | 100.00 | |
| mbx_tl_intg_err | 3.000s | 302.146us | 1 | 1 | 100.00 | |