Simulation Results: rom_ctrl

 
26/11/2025 16:02:05 sha: 2b9f4df json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 95.10 %
  • code
  • 97.96 %
  • assert
  • 96.65 %
  • func
  • 90.69 %
  • line
  • 99.32 %
  • branch
  • 98.91 %
  • cond
  • 98.22 %
  • toggle
  • 100.00 %
  • FSM
  • 93.33 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
rom_ctrl_smoke 3.920s 1856.490us 1 1 100.00
csr_hw_reset 1 1 100.00
rom_ctrl_csr_hw_reset 5.370s 192.402us 1 1 100.00
csr_rw 1 1 100.00
rom_ctrl_csr_rw 3.780s 123.593us 1 1 100.00
csr_bit_bash 1 1 100.00
rom_ctrl_csr_bit_bash 4.360s 127.320us 1 1 100.00
csr_aliasing 1 1 100.00
rom_ctrl_csr_aliasing 4.620s 166.869us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
rom_ctrl_csr_mem_rw_with_rand_reset 3.590s 629.546us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
rom_ctrl_csr_rw 3.780s 123.593us 1 1 100.00
rom_ctrl_csr_aliasing 4.620s 166.869us 1 1 100.00
mem_walk 1 1 100.00
rom_ctrl_mem_walk 3.090s 370.856us 1 1 100.00
mem_partial_access 1 1 100.00
rom_ctrl_mem_partial_access 3.500s 132.479us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
max_throughput_chk 1 1 100.00
rom_ctrl_max_throughput_chk 4.960s 177.582us 1 1 100.00
stress_all 1 1 100.00
rom_ctrl_stress_all 12.320s 460.854us 1 1 100.00
kmac_err_chk 1 1 100.00
rom_ctrl_kmac_err_chk 7.070s 1083.177us 1 1 100.00
alert_test 1 1 100.00
rom_ctrl_alert_test 4.140s 1805.757us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
rom_ctrl_tl_errors 5.150s 655.760us 1 1 100.00
tl_d_illegal_access 1 1 100.00
rom_ctrl_tl_errors 5.150s 655.760us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
rom_ctrl_csr_hw_reset 5.370s 192.402us 1 1 100.00
rom_ctrl_csr_rw 3.780s 123.593us 1 1 100.00
rom_ctrl_csr_aliasing 4.620s 166.869us 1 1 100.00
rom_ctrl_same_csr_outstanding 3.280s 370.785us 1 1 100.00
tl_d_partial_access 4 4 100.00
rom_ctrl_csr_hw_reset 5.370s 192.402us 1 1 100.00
rom_ctrl_csr_rw 3.780s 123.593us 1 1 100.00
rom_ctrl_csr_aliasing 4.620s 166.869us 1 1 100.00
rom_ctrl_same_csr_outstanding 3.280s 370.785us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
corrupt_sig_fatal_chk 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 68.560s 10612.610us 1 1 100.00
passthru_mem_tl_intg_err 1 1 100.00
rom_ctrl_passthru_mem_tl_intg_err 19.940s 8737.364us 1 1 100.00
tl_intg_err 2 2 100.00
rom_ctrl_sec_cm 102.840s 538.422us 1 1 100.00
rom_ctrl_tl_intg_err 26.630s 689.964us 1 1 100.00
prim_fsm_check 1 1 100.00
rom_ctrl_sec_cm 102.840s 538.422us 1 1 100.00
prim_count_check 1 1 100.00
rom_ctrl_sec_cm 102.840s 538.422us 1 1 100.00
sec_cm_checker_ctr_consistency 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 68.560s 10612.610us 1 1 100.00
sec_cm_checker_ctrl_flow_consistency 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 68.560s 10612.610us 1 1 100.00
sec_cm_checker_fsm_local_esc 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 68.560s 10612.610us 1 1 100.00
sec_cm_compare_ctrl_flow_consistency 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 68.560s 10612.610us 1 1 100.00
sec_cm_compare_ctr_consistency 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 68.560s 10612.610us 1 1 100.00
sec_cm_compare_ctr_redun 1 1 100.00
rom_ctrl_sec_cm 102.840s 538.422us 1 1 100.00
sec_cm_fsm_sparse 1 1 100.00
rom_ctrl_sec_cm 102.840s 538.422us 1 1 100.00
sec_cm_mem_scramble 1 1 100.00
rom_ctrl_smoke 3.920s 1856.490us 1 1 100.00
sec_cm_mem_digest 1 1 100.00
rom_ctrl_smoke 3.920s 1856.490us 1 1 100.00
sec_cm_intersig_mubi 1 1 100.00
rom_ctrl_smoke 3.920s 1856.490us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
rom_ctrl_tl_intg_err 26.630s 689.964us 1 1 100.00
sec_cm_bus_local_esc 2 2 100.00
rom_ctrl_corrupt_sig_fatal_chk 68.560s 10612.610us 1 1 100.00
rom_ctrl_kmac_err_chk 7.070s 1083.177us 1 1 100.00
sec_cm_mux_mubi 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 68.560s 10612.610us 1 1 100.00
sec_cm_mux_consistency 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 68.560s 10612.610us 1 1 100.00
sec_cm_ctrl_redun 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 68.560s 10612.610us 1 1 100.00
sec_cm_ctrl_mem_integrity 1 1 100.00
rom_ctrl_passthru_mem_tl_intg_err 19.940s 8737.364us 1 1 100.00
sec_cm_tlul_fifo_ctr_redun 1 1 100.00
rom_ctrl_sec_cm 102.840s 538.422us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
rom_ctrl_stress_all_with_rand_reset 76.140s 11475.771us 1 1 100.00