Simulation Results: rom_ctrl

 
26/11/2025 16:02:05 sha: 2b9f4df json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 97.26 %
  • code
  • 97.76 %
  • assert
  • 96.65 %
  • func
  • 97.37 %
  • line
  • 99.32 %
  • branch
  • 98.54 %
  • cond
  • 97.77 %
  • toggle
  • 99.85 %
  • FSM
  • 93.33 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
rom_ctrl_smoke 8.280s 296.748us 1 1 100.00
csr_hw_reset 1 1 100.00
rom_ctrl_csr_hw_reset 10.220s 210.632us 1 1 100.00
csr_rw 1 1 100.00
rom_ctrl_csr_rw 9.330s 2567.411us 1 1 100.00
csr_bit_bash 1 1 100.00
rom_ctrl_csr_bit_bash 7.110s 391.561us 1 1 100.00
csr_aliasing 1 1 100.00
rom_ctrl_csr_aliasing 5.800s 393.864us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
rom_ctrl_csr_mem_rw_with_rand_reset 7.190s 233.199us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
rom_ctrl_csr_rw 9.330s 2567.411us 1 1 100.00
rom_ctrl_csr_aliasing 5.800s 393.864us 1 1 100.00
mem_walk 1 1 100.00
rom_ctrl_mem_walk 6.870s 2783.236us 1 1 100.00
mem_partial_access 1 1 100.00
rom_ctrl_mem_partial_access 5.950s 214.213us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
max_throughput_chk 1 1 100.00
rom_ctrl_max_throughput_chk 6.570s 2895.213us 1 1 100.00
stress_all 1 1 100.00
rom_ctrl_stress_all 28.190s 6752.831us 1 1 100.00
kmac_err_chk 1 1 100.00
rom_ctrl_kmac_err_chk 12.790s 383.009us 1 1 100.00
alert_test 1 1 100.00
rom_ctrl_alert_test 7.500s 297.030us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
rom_ctrl_tl_errors 10.860s 212.473us 1 1 100.00
tl_d_illegal_access 1 1 100.00
rom_ctrl_tl_errors 10.860s 212.473us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
rom_ctrl_csr_hw_reset 10.220s 210.632us 1 1 100.00
rom_ctrl_csr_rw 9.330s 2567.411us 1 1 100.00
rom_ctrl_csr_aliasing 5.800s 393.864us 1 1 100.00
rom_ctrl_same_csr_outstanding 6.480s 207.051us 1 1 100.00
tl_d_partial_access 4 4 100.00
rom_ctrl_csr_hw_reset 10.220s 210.632us 1 1 100.00
rom_ctrl_csr_rw 9.330s 2567.411us 1 1 100.00
rom_ctrl_csr_aliasing 5.800s 393.864us 1 1 100.00
rom_ctrl_same_csr_outstanding 6.480s 207.051us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
corrupt_sig_fatal_chk 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 146.430s 3033.518us 1 1 100.00
passthru_mem_tl_intg_err 1 1 100.00
rom_ctrl_passthru_mem_tl_intg_err 36.440s 16505.641us 1 1 100.00
tl_intg_err 2 2 100.00
rom_ctrl_sec_cm 461.250s 1154.592us 1 1 100.00
rom_ctrl_tl_intg_err 53.290s 541.257us 1 1 100.00
prim_fsm_check 1 1 100.00
rom_ctrl_sec_cm 461.250s 1154.592us 1 1 100.00
prim_count_check 1 1 100.00
rom_ctrl_sec_cm 461.250s 1154.592us 1 1 100.00
sec_cm_checker_ctr_consistency 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 146.430s 3033.518us 1 1 100.00
sec_cm_checker_ctrl_flow_consistency 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 146.430s 3033.518us 1 1 100.00
sec_cm_checker_fsm_local_esc 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 146.430s 3033.518us 1 1 100.00
sec_cm_compare_ctrl_flow_consistency 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 146.430s 3033.518us 1 1 100.00
sec_cm_compare_ctr_consistency 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 146.430s 3033.518us 1 1 100.00
sec_cm_compare_ctr_redun 1 1 100.00
rom_ctrl_sec_cm 461.250s 1154.592us 1 1 100.00
sec_cm_fsm_sparse 1 1 100.00
rom_ctrl_sec_cm 461.250s 1154.592us 1 1 100.00
sec_cm_mem_scramble 1 1 100.00
rom_ctrl_smoke 8.280s 296.748us 1 1 100.00
sec_cm_mem_digest 1 1 100.00
rom_ctrl_smoke 8.280s 296.748us 1 1 100.00
sec_cm_intersig_mubi 1 1 100.00
rom_ctrl_smoke 8.280s 296.748us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
rom_ctrl_tl_intg_err 53.290s 541.257us 1 1 100.00
sec_cm_bus_local_esc 2 2 100.00
rom_ctrl_corrupt_sig_fatal_chk 146.430s 3033.518us 1 1 100.00
rom_ctrl_kmac_err_chk 12.790s 383.009us 1 1 100.00
sec_cm_mux_mubi 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 146.430s 3033.518us 1 1 100.00
sec_cm_mux_consistency 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 146.430s 3033.518us 1 1 100.00
sec_cm_ctrl_redun 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 146.430s 3033.518us 1 1 100.00
sec_cm_ctrl_mem_integrity 1 1 100.00
rom_ctrl_passthru_mem_tl_intg_err 36.440s 16505.641us 1 1 100.00
sec_cm_tlul_fifo_ctr_redun 1 1 100.00
rom_ctrl_sec_cm 461.250s 1154.592us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
rom_ctrl_stress_all_with_rand_reset 57.090s 2227.662us 1 1 100.00