Simulation Results: rstmgr

 
26/11/2025 16:02:05 sha: 2b9f4df json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 98.22 %
  • code
  • 99.15 %
  • assert
  • 97.62 %
  • func
  • 97.89 %
  • line
  • 99.19 %
  • branch
  • 99.72 %
  • cond
  • 98.18 %
  • toggle
  • 99.52 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
rstmgr_smoke 1.510s 58.888us 1 1 100.00
csr_hw_reset 1 1 100.00
rstmgr_csr_hw_reset 0.960s 64.336us 1 1 100.00
csr_rw 1 1 100.00
rstmgr_csr_rw 0.890s 37.018us 1 1 100.00
csr_bit_bash 1 1 100.00
rstmgr_csr_bit_bash 5.070s 198.448us 1 1 100.00
csr_aliasing 1 1 100.00
rstmgr_csr_aliasing 1.010s 43.624us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
rstmgr_csr_mem_rw_with_rand_reset 1.010s 67.177us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
rstmgr_csr_rw 0.890s 37.018us 1 1 100.00
rstmgr_csr_aliasing 1.010s 43.624us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
reset_stretcher 1 1 100.00
rstmgr_por_stretcher 1.330s 139.881us 1 1 100.00
sw_rst 1 1 100.00
rstmgr_sw_rst 1.240s 45.664us 1 1 100.00
sw_rst_reset_race 1 1 100.00
rstmgr_sw_rst_reset_race 1.090s 72.807us 1 1 100.00
reset_info 1 1 100.00
rstmgr_reset 4.740s 561.340us 1 1 100.00
cpu_info 1 1 100.00
rstmgr_reset 4.740s 561.340us 1 1 100.00
alert_info 1 1 100.00
rstmgr_reset 4.740s 561.340us 1 1 100.00
reset_info_capture 1 1 100.00
rstmgr_reset 4.740s 561.340us 1 1 100.00
stress_all 1 1 100.00
rstmgr_stress_all 33.150s 3942.290us 1 1 100.00
alert_test 1 1 100.00
rstmgr_alert_test 1.070s 38.358us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
rstmgr_tl_errors 1.380s 40.333us 1 1 100.00
tl_d_illegal_access 1 1 100.00
rstmgr_tl_errors 1.380s 40.333us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
rstmgr_csr_hw_reset 0.960s 64.336us 1 1 100.00
rstmgr_csr_rw 0.890s 37.018us 1 1 100.00
rstmgr_csr_aliasing 1.010s 43.624us 1 1 100.00
rstmgr_same_csr_outstanding 0.950s 37.153us 1 1 100.00
tl_d_partial_access 4 4 100.00
rstmgr_csr_hw_reset 0.960s 64.336us 1 1 100.00
rstmgr_csr_rw 0.890s 37.018us 1 1 100.00
rstmgr_csr_aliasing 1.010s 43.624us 1 1 100.00
rstmgr_same_csr_outstanding 0.950s 37.153us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
rstmgr_tl_intg_err 3.930s 632.820us 1 1 100.00
rstmgr_sec_cm 16.840s 3399.713us 1 1 100.00
prim_count_check 1 1 100.00
rstmgr_sec_cm 16.840s 3399.713us 1 1 100.00
prim_fsm_check 1 1 100.00
rstmgr_sec_cm 16.840s 3399.713us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
rstmgr_tl_intg_err 3.930s 632.820us 1 1 100.00
sec_cm_scan_intersig_mubi 1 1 100.00
rstmgr_sec_cm_scan_intersig_mubi 1.000s 65.760us 1 1 100.00
sec_cm_leaf_rst_bkgn_chk 1 1 100.00
rstmgr_leaf_rst_cnsty 3.690s 418.190us 1 1 100.00
sec_cm_leaf_rst_shadow 1 1 100.00
rstmgr_leaf_rst_shadow_attack 2.060s 291.957us 1 1 100.00
sec_cm_leaf_fsm_sparse 1 1 100.00
rstmgr_sec_cm 16.840s 3399.713us 1 1 100.00
sec_cm_sw_rst_config_regwen 1 1 100.00
rstmgr_csr_rw 0.890s 37.018us 1 1 100.00
sec_cm_dump_ctrl_config_regwen 1 1 100.00
rstmgr_csr_rw 0.890s 37.018us 1 1 100.00