Simulation Results: rv_dm

 
26/11/2025 16:02:05 sha: 2b9f4df json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 78.15 %
  • code
  • 72.38 %
  • assert
  • 96.16 %
  • func
  • 65.90 %
  • line
  • 90.22 %
  • branch
  • 74.57 %
  • cond
  • 73.82 %
  • toggle
  • 70.15 %
  • FSM
  • 53.12 %
Validation stages
V1
90.32%
V2
60.71%
V2S
75.00%
V3
0.00%
unmapped
0.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 0 1 0.00
rv_dm_smoke 9.310s 11108.303us 0 1 0.00
jtag_dtm_csr_hw_reset 1 1 100.00
rv_dm_jtag_dtm_csr_hw_reset 1.250s 370.350us 1 1 100.00
jtag_dtm_csr_rw 1 1 100.00
rv_dm_jtag_dtm_csr_rw 0.920s 382.104us 1 1 100.00
jtag_dtm_csr_bit_bash 1 1 100.00
rv_dm_jtag_dtm_csr_bit_bash 6.890s 6762.202us 1 1 100.00
jtag_dtm_csr_aliasing 1 1 100.00
rv_dm_jtag_dtm_csr_aliasing 0.850s 235.488us 1 1 100.00
jtag_dmi_csr_hw_reset 1 1 100.00
rv_dm_jtag_dmi_csr_hw_reset 4.060s 3858.798us 1 1 100.00
jtag_dmi_csr_rw 1 1 100.00
rv_dm_jtag_dmi_csr_rw 4.480s 1935.941us 1 1 100.00
jtag_dmi_csr_bit_bash 1 1 100.00
rv_dm_jtag_dmi_csr_bit_bash 9.660s 5242.065us 1 1 100.00
jtag_dmi_csr_aliasing 1 1 100.00
rv_dm_jtag_dmi_csr_aliasing 61.070s 32863.091us 1 1 100.00
jtag_dmi_cmderr_busy 1 1 100.00
rv_dm_cmderr_busy 2.550s 994.558us 1 1 100.00
jtag_dmi_cmderr_not_supported 1 1 100.00
rv_dm_cmderr_not_supported 0.700s 177.938us 1 1 100.00
cmderr_exception 1 1 100.00
rv_dm_cmderr_exception 0.860s 225.907us 1 1 100.00
mem_tl_access_resuming 0 1 0.00
rv_dm_mem_tl_access_resuming 0.880s 103.964us 0 1 0.00
mem_tl_access_halted 1 1 100.00
rv_dm_mem_tl_access_halted 0.700s 126.949us 1 1 100.00
cmderr_halt_resume 1 1 100.00
rv_dm_cmderr_halt_resume 1.160s 854.852us 1 1 100.00
dataaddr_rw_access 1 1 100.00
rv_dm_dataaddr_rw_access 1.180s 343.466us 1 1 100.00
halt_resume 1 1 100.00
rv_dm_halt_resume_whereto 1.120s 464.418us 1 1 100.00
progbuf_busy 1 1 100.00
rv_dm_cmderr_busy 2.550s 994.558us 1 1 100.00
abstractcmd_status 1 1 100.00
rv_dm_abstractcmd_status 1.110s 230.110us 1 1 100.00
progbuf_read_write_execute 1 1 100.00
rv_dm_progbuf_read_write_execute 1.400s 354.521us 1 1 100.00
progbuf_exception 1 1 100.00
rv_dm_cmderr_exception 0.860s 225.907us 1 1 100.00
rom_read_access 1 1 100.00
rv_dm_rom_read_access 0.710s 63.781us 1 1 100.00
csr_hw_reset 1 1 100.00
rv_dm_csr_hw_reset 1.760s 258.315us 1 1 100.00
csr_rw 1 1 100.00
rv_dm_csr_rw 1.250s 79.901us 1 1 100.00
csr_bit_bash 1 1 100.00
rv_dm_csr_bit_bash 35.370s 2876.013us 1 1 100.00
csr_aliasing 1 1 100.00
rv_dm_csr_aliasing 48.040s 17004.344us 1 1 100.00
csr_mem_rw_with_rand_reset 0 1 0.00
rv_dm_csr_mem_rw_with_rand_reset 0.670s 54.780us 0 1 0.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
rv_dm_csr_aliasing 48.040s 17004.344us 1 1 100.00
rv_dm_csr_rw 1.250s 79.901us 1 1 100.00
mem_walk 1 1 100.00
rv_dm_mem_walk 0.650s 73.723us 1 1 100.00
mem_partial_access 1 1 100.00
rv_dm_mem_partial_access 0.810s 92.754us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
idcode 0 1 0.00
rv_dm_smoke 9.310s 11108.303us 0 1 0.00
jtag_dtm_hard_reset 1 1 100.00
rv_dm_jtag_dtm_hard_reset 0.960s 369.932us 1 1 100.00
jtag_dtm_idle_hint 1 1 100.00
rv_dm_jtag_dtm_idle_hint 1.070s 597.728us 1 1 100.00
jtag_dmi_failed_op 1 1 100.00
rv_dm_dmi_failed_op 1.220s 310.769us 1 1 100.00
jtag_dmi_dm_inactive 1 1 100.00
rv_dm_jtag_dmi_dm_inactive 1.290s 750.424us 1 1 100.00
sba 0 2 0.00
rv_dm_sba_tl_access 250.680s 300000.000us 0 1 0.00
rv_dm_delayed_resp_sba_tl_access 127.380s 300000.000us 0 1 0.00
bad_sba 0 1 0.00
rv_dm_bad_sba_tl_access 525.550s 300000.000us 0 1 0.00
sba_autoincrement 0 1 0.00
rv_dm_autoincr_sba_tl_access 528.230s 300000.000us 0 1 0.00
jtag_dmi_debug_disabled 0 1 0.00
rv_dm_jtag_dmi_debug_disabled 0.680s 106.631us 0 1 0.00
sba_debug_disabled 1 1 100.00
rv_dm_sba_debug_disabled 10.280s 5914.094us 1 1 100.00
ndmreset_req 1 1 100.00
rv_dm_ndmreset_req 0.740s 185.124us 1 1 100.00
hart_unavail 0 1 0.00
rv_dm_hart_unavail 0.700s 58.437us 0 1 0.00
tap_ctrl_transitions 1 2 50.00
rv_dm_tap_fsm_rand_reset 0.710s 17.207us 0 1 0.00
rv_dm_tap_fsm 14.550s 7792.796us 1 1 100.00
hartsel_warl 1 1 100.00
rv_dm_hartsel_warl 0.670s 58.196us 1 1 100.00
stress_all 0 1 0.00
rv_dm_stress_all 8690.120s 10000000.000us 0 1 0.00
alert_test 1 1 100.00
rv_dm_alert_test 0.880s 182.848us 1 1 100.00
tl_d_oob_addr_access 0 1 0.00
rv_dm_tl_errors 0.680s 37.093us 0 1 0.00
tl_d_illegal_access 0 1 0.00
rv_dm_tl_errors 0.680s 37.093us 0 1 0.00
tl_d_outstanding_access 4 4 100.00
rv_dm_csr_aliasing 48.040s 17004.344us 1 1 100.00
rv_dm_csr_hw_reset 1.760s 258.315us 1 1 100.00
rv_dm_csr_rw 1.250s 79.901us 1 1 100.00
rv_dm_same_csr_outstanding 5.630s 520.337us 1 1 100.00
tl_d_partial_access 4 4 100.00
rv_dm_csr_aliasing 48.040s 17004.344us 1 1 100.00
rv_dm_csr_hw_reset 1.760s 258.315us 1 1 100.00
rv_dm_csr_rw 1.250s 79.901us 1 1 100.00
rv_dm_same_csr_outstanding 5.630s 520.337us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
rv_dm_tl_intg_err 12.010s 2691.460us 1 1 100.00
rv_dm_sec_cm 2.200s 1096.362us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
rv_dm_tl_intg_err 12.010s 2691.460us 1 1 100.00
sec_cm_lc_hw_debug_en_intersig_mubi 2 2 100.00
rv_dm_sba_debug_disabled 10.280s 5914.094us 1 1 100.00
rv_dm_debug_disabled 0.790s 36.526us 1 1 100.00
sec_cm_lc_dft_en_intersig_mubi 2 2 100.00
rv_dm_sba_debug_disabled 10.280s 5914.094us 1 1 100.00
rv_dm_debug_disabled 0.790s 36.526us 1 1 100.00
sec_cm_otp_dis_rv_dm_late_debug_intersig_mubi 0 1 0.00
rv_dm_smoke 9.310s 11108.303us 0 1 0.00
sec_cm_dm_en_ctrl_lc_gated 0 1 0.00
rv_dm_buffered_enable 0.770s 95.201us 0 1 0.00
sec_cm_sba_tl_lc_gate_fsm_sparse 1 1 100.00
rv_dm_sparse_lc_gate_fsm 0.950s 275.855us 1 1 100.00
sec_cm_mem_tl_lc_gate_fsm_sparse 1 1 100.00
rv_dm_sparse_lc_gate_fsm 0.950s 275.855us 1 1 100.00
sec_cm_exec_ctrl_mubi 0 1 0.00
rv_dm_buffered_enable 0.770s 95.201us 0 1 0.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 0 1 0.00
rv_dm_stress_all_with_rand_reset 0.710s 30.463us 0 1 0.00
Testpoint Test Max Runtime Sim Time Pass Total %
Unmapped 0 1 0.00
rv_dm_scanmode 50.180s 300000.000us 0 1 0.00