Simulation Results: spi_device

 
26/11/2025 16:02:05 sha: 2b9f4df json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 87.10 %
  • code
  • 93.18 %
  • assert
  • 94.30 %
  • func
  • 73.81 %
  • line
  • 99.03 %
  • branch
  • 98.23 %
  • cond
  • 95.75 %
  • toggle
  • 83.54 %
  • FSM
  • 89.36 %
Validation stages
V1
100.00%
V2
96.15%
V2S
100.00%
unmapped
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
spi_device_flash_and_tpm 92.430s 64258.961us 1 1 100.00
csr_hw_reset 1 1 100.00
spi_device_csr_hw_reset 1.100s 35.935us 1 1 100.00
csr_rw 1 1 100.00
spi_device_csr_rw 1.940s 266.486us 1 1 100.00
csr_bit_bash 1 1 100.00
spi_device_csr_bit_bash 27.790s 15019.703us 1 1 100.00
csr_aliasing 1 1 100.00
spi_device_csr_aliasing 10.050s 936.386us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
spi_device_csr_mem_rw_with_rand_reset 2.990s 202.960us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
spi_device_csr_rw 1.940s 266.486us 1 1 100.00
spi_device_csr_aliasing 10.050s 936.386us 1 1 100.00
mem_walk 1 1 100.00
spi_device_mem_walk 0.760s 17.488us 1 1 100.00
mem_partial_access 1 1 100.00
spi_device_mem_partial_access 1.640s 26.742us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
csb_read 1 1 100.00
spi_device_csb_read 1.010s 69.451us 1 1 100.00
mem_parity 0 1 0.00
spi_device_mem_parity 0.950s 1.377us 0 1 0.00
mem_cfg 0 1 0.00
spi_device_ram_cfg 0.780s 8.630us 0 1 0.00
tpm_read 1 1 100.00
spi_device_tpm_rw 1.370s 33.386us 1 1 100.00
tpm_write 1 1 100.00
spi_device_tpm_rw 1.370s 33.386us 1 1 100.00
tpm_hw_reg 2 2 100.00
spi_device_tpm_read_hw_reg 3.240s 1269.992us 1 1 100.00
spi_device_tpm_sts_read 1.180s 153.924us 1 1 100.00
tpm_fully_random_case 1 1 100.00
spi_device_tpm_all 15.130s 7721.052us 1 1 100.00
pass_cmd_filtering 2 2 100.00
spi_device_pass_cmd_filtering 15.930s 10033.260us 1 1 100.00
spi_device_flash_all 114.190s 17733.989us 1 1 100.00
pass_addr_translation 2 2 100.00
spi_device_pass_addr_payload_swap 7.770s 6197.067us 1 1 100.00
spi_device_flash_all 114.190s 17733.989us 1 1 100.00
pass_payload_translation 2 2 100.00
spi_device_pass_addr_payload_swap 7.770s 6197.067us 1 1 100.00
spi_device_flash_all 114.190s 17733.989us 1 1 100.00
cmd_info_slots 1 1 100.00
spi_device_flash_all 114.190s 17733.989us 1 1 100.00
cmd_read_status 2 2 100.00
spi_device_intercept 2.260s 76.057us 1 1 100.00
spi_device_flash_all 114.190s 17733.989us 1 1 100.00
cmd_read_jedec 2 2 100.00
spi_device_intercept 2.260s 76.057us 1 1 100.00
spi_device_flash_all 114.190s 17733.989us 1 1 100.00
cmd_read_sfdp 2 2 100.00
spi_device_intercept 2.260s 76.057us 1 1 100.00
spi_device_flash_all 114.190s 17733.989us 1 1 100.00
cmd_fast_read 2 2 100.00
spi_device_intercept 2.260s 76.057us 1 1 100.00
spi_device_flash_all 114.190s 17733.989us 1 1 100.00
cmd_read_pipeline 2 2 100.00
spi_device_intercept 2.260s 76.057us 1 1 100.00
spi_device_flash_all 114.190s 17733.989us 1 1 100.00
flash_cmd_upload 1 1 100.00
spi_device_upload 3.540s 419.789us 1 1 100.00
mailbox_command 1 1 100.00
spi_device_mailbox 6.620s 396.666us 1 1 100.00
mailbox_cross_outside_command 1 1 100.00
spi_device_mailbox 6.620s 396.666us 1 1 100.00
mailbox_cross_inside_command 1 1 100.00
spi_device_mailbox 6.620s 396.666us 1 1 100.00
cmd_read_buffer 2 2 100.00
spi_device_flash_mode 5.760s 704.430us 1 1 100.00
spi_device_read_buffer_direct 3.320s 440.776us 1 1 100.00
cmd_dummy_cycle 2 2 100.00
spi_device_mailbox 6.620s 396.666us 1 1 100.00
spi_device_flash_all 114.190s 17733.989us 1 1 100.00
quad_spi 1 1 100.00
spi_device_flash_all 114.190s 17733.989us 1 1 100.00
dual_spi 1 1 100.00
spi_device_flash_all 114.190s 17733.989us 1 1 100.00
4b_3b_feature 1 1 100.00
spi_device_cfg_cmd 2.430s 47.889us 1 1 100.00
write_enable_disable 1 1 100.00
spi_device_cfg_cmd 2.430s 47.889us 1 1 100.00
TPM_with_flash_or_passthrough_mode 1 1 100.00
spi_device_flash_and_tpm 92.430s 64258.961us 1 1 100.00
tpm_and_flash_trans_with_min_inactive_time 1 1 100.00
spi_device_flash_and_tpm_min_idle 240.680s 163952.579us 1 1 100.00
stress_all 1 1 100.00
spi_device_stress_all 83.100s 13705.846us 1 1 100.00
alert_test 1 1 100.00
spi_device_alert_test 0.660s 14.960us 1 1 100.00
intr_test 1 1 100.00
spi_device_intr_test 0.870s 87.324us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
spi_device_tl_errors 3.410s 74.288us 1 1 100.00
tl_d_illegal_access 1 1 100.00
spi_device_tl_errors 3.410s 74.288us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
spi_device_csr_hw_reset 1.100s 35.935us 1 1 100.00
spi_device_csr_rw 1.940s 266.486us 1 1 100.00
spi_device_csr_aliasing 10.050s 936.386us 1 1 100.00
spi_device_same_csr_outstanding 2.270s 264.027us 1 1 100.00
tl_d_partial_access 4 4 100.00
spi_device_csr_hw_reset 1.100s 35.935us 1 1 100.00
spi_device_csr_rw 1.940s 266.486us 1 1 100.00
spi_device_csr_aliasing 10.050s 936.386us 1 1 100.00
spi_device_same_csr_outstanding 2.270s 264.027us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
spi_device_tl_intg_err 16.110s 3925.587us 1 1 100.00
spi_device_sec_cm 1.090s 113.111us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
spi_device_tl_intg_err 16.110s 3925.587us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
Unmapped 1 1 100.00
spi_device_flash_mode_ignore_cmds 183.990s 38856.157us 1 1 100.00