Simulation Results: spi_host

 
26/11/2025 16:02:05 sha: 2b9f4df json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 92.02 %
  • code
  • 95.02 %
  • assert
  • 93.54 %
  • func
  • 87.50 %
  • block
  • 96.82 %
  • line
  • 98.69 %
  • branch
  • 93.35 %
  • toggle
  • 88.02 %
  • FSM
  • 100.00 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
unmapped
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
spi_host_smoke 13.000s 422.128us 1 1 100.00
csr_hw_reset 1 1 100.00
spi_host_csr_hw_reset 1.000s 160.539us 1 1 100.00
csr_rw 1 1 100.00
spi_host_csr_rw 1.000s 52.812us 1 1 100.00
csr_bit_bash 1 1 100.00
spi_host_csr_bit_bash 3.000s 843.531us 1 1 100.00
csr_aliasing 1 1 100.00
spi_host_csr_aliasing 2.000s 19.907us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
spi_host_csr_mem_rw_with_rand_reset 1.000s 71.643us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
spi_host_csr_rw 1.000s 52.812us 1 1 100.00
spi_host_csr_aliasing 2.000s 19.907us 1 1 100.00
mem_walk 1 1 100.00
spi_host_mem_walk 2.000s 14.955us 1 1 100.00
mem_partial_access 1 1 100.00
spi_host_mem_partial_access 1.000s 45.837us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
performance 1 1 100.00
spi_host_performance 6.000s 22.536us 1 1 100.00
error_event_intr 3 3 100.00
spi_host_overflow_underflow 5.000s 112.278us 1 1 100.00
spi_host_error_cmd 2.000s 28.677us 1 1 100.00
spi_host_event 25.000s 3764.278us 1 1 100.00
clock_rate 1 1 100.00
spi_host_speed 8.000s 44.827us 1 1 100.00
speed 1 1 100.00
spi_host_speed 8.000s 44.827us 1 1 100.00
chip_select_timing 1 1 100.00
spi_host_speed 8.000s 44.827us 1 1 100.00
sw_reset 1 1 100.00
spi_host_sw_reset 8.000s 207.147us 1 1 100.00
passthrough_mode 1 1 100.00
spi_host_passthrough_mode 1.000s 29.378us 1 1 100.00
cpol_cpha 1 1 100.00
spi_host_speed 8.000s 44.827us 1 1 100.00
full_cycle 1 1 100.00
spi_host_speed 8.000s 44.827us 1 1 100.00
duplex 1 1 100.00
spi_host_smoke 13.000s 422.128us 1 1 100.00
tx_rx_only 1 1 100.00
spi_host_smoke 13.000s 422.128us 1 1 100.00
stress_all 1 1 100.00
spi_host_stress_all 2.000s 107.329us 1 1 100.00
spien 1 1 100.00
spi_host_spien 7.000s 460.559us 1 1 100.00
stall 1 1 100.00
spi_host_status_stall 381.000s 47900.018us 1 1 100.00
Idlecsbactive 1 1 100.00
spi_host_idlecsbactive 9.000s 1544.183us 1 1 100.00
data_fifo_status 1 1 100.00
spi_host_overflow_underflow 5.000s 112.278us 1 1 100.00
alert_test 1 1 100.00
spi_host_alert_test 1.000s 15.592us 1 1 100.00
intr_test 1 1 100.00
spi_host_intr_test 2.000s 17.303us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
spi_host_tl_errors 2.000s 87.004us 1 1 100.00
tl_d_illegal_access 1 1 100.00
spi_host_tl_errors 2.000s 87.004us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
spi_host_csr_hw_reset 1.000s 160.539us 1 1 100.00
spi_host_csr_rw 1.000s 52.812us 1 1 100.00
spi_host_csr_aliasing 2.000s 19.907us 1 1 100.00
spi_host_same_csr_outstanding 1.000s 28.247us 1 1 100.00
tl_d_partial_access 4 4 100.00
spi_host_csr_hw_reset 1.000s 160.539us 1 1 100.00
spi_host_csr_rw 1.000s 52.812us 1 1 100.00
spi_host_csr_aliasing 2.000s 19.907us 1 1 100.00
spi_host_same_csr_outstanding 1.000s 28.247us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
spi_host_sec_cm 1.000s 159.197us 1 1 100.00
spi_host_tl_intg_err 2.000s 99.688us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
spi_host_tl_intg_err 2.000s 99.688us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
Unmapped 1 1 100.00
spi_host_upper_range_clkdiv 264.000s 25873.277us 1 1 100.00