Simulation Results: sram_ctrl

 
26/11/2025 16:02:05 sha: 2b9f4df json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 94.29 %
  • code
  • 93.73 %
  • assert
  • 95.83 %
  • func
  • 93.32 %
  • line
  • 98.66 %
  • branch
  • 96.78 %
  • cond
  • 92.04 %
  • toggle
  • 90.71 %
  • FSM
  • 90.48 %
Validation stages
V1
100.00%
V2
100.00%
V2S
75.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
sram_ctrl_smoke 5.320s 777.438us 1 1 100.00
csr_hw_reset 1 1 100.00
sram_ctrl_csr_hw_reset 0.890s 13.756us 1 1 100.00
csr_rw 1 1 100.00
sram_ctrl_csr_rw 0.780s 18.143us 1 1 100.00
csr_bit_bash 1 1 100.00
sram_ctrl_csr_bit_bash 2.320s 711.409us 1 1 100.00
csr_aliasing 1 1 100.00
sram_ctrl_csr_aliasing 0.890s 61.871us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
sram_ctrl_csr_mem_rw_with_rand_reset 2.680s 1397.822us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
sram_ctrl_csr_rw 0.780s 18.143us 1 1 100.00
sram_ctrl_csr_aliasing 0.890s 61.871us 1 1 100.00
mem_walk 1 1 100.00
sram_ctrl_mem_walk 183.980s 3945.723us 1 1 100.00
mem_partial_access 1 1 100.00
sram_ctrl_mem_partial_access 62.770s 2685.535us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
multiple_keys 1 1 100.00
sram_ctrl_multiple_keys 913.350s 47758.456us 1 1 100.00
stress_pipeline 1 1 100.00
sram_ctrl_stress_pipeline 192.200s 16859.324us 1 1 100.00
bijection 1 1 100.00
sram_ctrl_bijection 903.350s 62063.443us 1 1 100.00
access_during_key_req 1 1 100.00
sram_ctrl_access_during_key_req 298.840s 159987.541us 1 1 100.00
lc_escalation 1 1 100.00
sram_ctrl_lc_escalation 31.560s 15721.630us 1 1 100.00
executable 1 1 100.00
sram_ctrl_executable 214.190s 3892.735us 1 1 100.00
partial_access 2 2 100.00
sram_ctrl_partial_access 46.260s 1717.869us 1 1 100.00
sram_ctrl_partial_access_b2b 274.070s 8621.653us 1 1 100.00
max_throughput 3 3 100.00
sram_ctrl_max_throughput 37.580s 4090.465us 1 1 100.00
sram_ctrl_throughput_w_partial_write 62.480s 3265.106us 1 1 100.00
sram_ctrl_throughput_w_readback 7.630s 723.222us 1 1 100.00
regwen 1 1 100.00
sram_ctrl_regwen 367.780s 25947.068us 1 1 100.00
ram_cfg 1 1 100.00
sram_ctrl_ram_cfg 3.790s 3726.881us 1 1 100.00
stress_all 1 1 100.00
sram_ctrl_stress_all 3568.600s 308109.662us 1 1 100.00
alert_test 1 1 100.00
sram_ctrl_alert_test 0.900s 15.676us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
sram_ctrl_tl_errors 3.380s 475.223us 1 1 100.00
tl_d_illegal_access 1 1 100.00
sram_ctrl_tl_errors 3.380s 475.223us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
sram_ctrl_csr_hw_reset 0.890s 13.756us 1 1 100.00
sram_ctrl_csr_rw 0.780s 18.143us 1 1 100.00
sram_ctrl_csr_aliasing 0.890s 61.871us 1 1 100.00
sram_ctrl_same_csr_outstanding 0.880s 26.006us 1 1 100.00
tl_d_partial_access 4 4 100.00
sram_ctrl_csr_hw_reset 0.890s 13.756us 1 1 100.00
sram_ctrl_csr_rw 0.780s 18.143us 1 1 100.00
sram_ctrl_csr_aliasing 0.890s 61.871us 1 1 100.00
sram_ctrl_same_csr_outstanding 0.880s 26.006us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
passthru_mem_tl_intg_err 1 1 100.00
sram_ctrl_passthru_mem_tl_intg_err 66.720s 140836.995us 1 1 100.00
tl_intg_err 1 2 50.00
sram_ctrl_tl_intg_err 2.040s 382.020us 1 1 100.00
sram_ctrl_sec_cm 0.910s 2.054us 0 1 0.00
prim_count_check 0 1 0.00
sram_ctrl_sec_cm 0.910s 2.054us 0 1 0.00
sec_cm_bus_integrity 1 1 100.00
sram_ctrl_tl_intg_err 2.040s 382.020us 1 1 100.00
sec_cm_ctrl_config_regwen 1 1 100.00
sram_ctrl_regwen 367.780s 25947.068us 1 1 100.00
sec_cm_readback_config_regwen 1 1 100.00
sram_ctrl_regwen 367.780s 25947.068us 1 1 100.00
sec_cm_exec_config_regwen 1 1 100.00
sram_ctrl_csr_rw 0.780s 18.143us 1 1 100.00
sec_cm_exec_config_mubi 1 1 100.00
sram_ctrl_executable 214.190s 3892.735us 1 1 100.00
sec_cm_exec_intersig_mubi 1 1 100.00
sram_ctrl_executable 214.190s 3892.735us 1 1 100.00
sec_cm_lc_hw_debug_en_intersig_mubi 1 1 100.00
sram_ctrl_executable 214.190s 3892.735us 1 1 100.00
sec_cm_lc_escalate_en_intersig_mubi 1 1 100.00
sram_ctrl_lc_escalation 31.560s 15721.630us 1 1 100.00
sec_cm_prim_ram_ctrl_mubi 1 1 100.00
sram_ctrl_mubi_enc_err 3.720s 674.017us 1 1 100.00
sec_cm_mem_integrity 1 1 100.00
sram_ctrl_passthru_mem_tl_intg_err 66.720s 140836.995us 1 1 100.00
sec_cm_mem_readback 1 1 100.00
sram_ctrl_readback_err 8.700s 2776.923us 1 1 100.00
sec_cm_mem_scramble 1 1 100.00
sram_ctrl_smoke 5.320s 777.438us 1 1 100.00
sec_cm_addr_scramble 1 1 100.00
sram_ctrl_smoke 5.320s 777.438us 1 1 100.00
sec_cm_instr_bus_lc_gated 1 1 100.00
sram_ctrl_executable 214.190s 3892.735us 1 1 100.00
sec_cm_ram_tl_lc_gate_fsm_sparse 0 1 0.00
sram_ctrl_sec_cm 0.910s 2.054us 0 1 0.00
sec_cm_key_global_esc 1 1 100.00
sram_ctrl_lc_escalation 31.560s 15721.630us 1 1 100.00
sec_cm_key_local_esc 0 1 0.00
sram_ctrl_sec_cm 0.910s 2.054us 0 1 0.00
sec_cm_init_ctr_redun 0 1 0.00
sram_ctrl_sec_cm 0.910s 2.054us 0 1 0.00
sec_cm_scramble_key_sideload 1 1 100.00
sram_ctrl_smoke 5.320s 777.438us 1 1 100.00
sec_cm_tlul_fifo_ctr_redun 0 1 0.00
sram_ctrl_sec_cm 0.910s 2.054us 0 1 0.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
sram_ctrl_stress_all_with_rand_reset 6.960s 322.913us 1 1 100.00