Simulation Results: sram_ctrl

 
26/11/2025 16:02:05 sha: 2b9f4df json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 95.19 %
  • code
  • 95.90 %
  • assert
  • 95.79 %
  • func
  • 93.88 %
  • line
  • 99.07 %
  • branch
  • 97.47 %
  • cond
  • 92.29 %
  • toggle
  • 90.66 %
  • FSM
  • 100.00 %
Validation stages
V1
100.00%
V2
100.00%
V2S
75.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
sram_ctrl_smoke 9.620s 981.711us 1 1 100.00
csr_hw_reset 1 1 100.00
sram_ctrl_csr_hw_reset 0.670s 18.535us 1 1 100.00
csr_rw 1 1 100.00
sram_ctrl_csr_rw 0.810s 26.011us 1 1 100.00
csr_bit_bash 1 1 100.00
sram_ctrl_csr_bit_bash 0.990s 49.908us 1 1 100.00
csr_aliasing 1 1 100.00
sram_ctrl_csr_aliasing 0.670s 14.868us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
sram_ctrl_csr_mem_rw_with_rand_reset 0.980s 106.606us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
sram_ctrl_csr_rw 0.810s 26.011us 1 1 100.00
sram_ctrl_csr_aliasing 0.670s 14.868us 1 1 100.00
mem_walk 1 1 100.00
sram_ctrl_mem_walk 5.010s 338.071us 1 1 100.00
mem_partial_access 1 1 100.00
sram_ctrl_mem_partial_access 3.080s 227.561us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
multiple_keys 1 1 100.00
sram_ctrl_multiple_keys 327.750s 13502.082us 1 1 100.00
stress_pipeline 1 1 100.00
sram_ctrl_stress_pipeline 157.170s 8751.325us 1 1 100.00
bijection 1 1 100.00
sram_ctrl_bijection 26.230s 6541.391us 1 1 100.00
access_during_key_req 1 1 100.00
sram_ctrl_access_during_key_req 387.810s 5089.490us 1 1 100.00
lc_escalation 1 1 100.00
sram_ctrl_lc_escalation 7.860s 803.399us 1 1 100.00
executable 1 1 100.00
sram_ctrl_executable 40.410s 278.793us 1 1 100.00
partial_access 2 2 100.00
sram_ctrl_partial_access 6.780s 94.136us 1 1 100.00
sram_ctrl_partial_access_b2b 206.620s 3471.034us 1 1 100.00
max_throughput 3 3 100.00
sram_ctrl_max_throughput 37.880s 231.940us 1 1 100.00
sram_ctrl_throughput_w_partial_write 12.580s 192.642us 1 1 100.00
sram_ctrl_throughput_w_readback 41.330s 268.791us 1 1 100.00
regwen 1 1 100.00
sram_ctrl_regwen 371.020s 2719.602us 1 1 100.00
ram_cfg 1 1 100.00
sram_ctrl_ram_cfg 0.940s 173.168us 1 1 100.00
stress_all 1 1 100.00
sram_ctrl_stress_all 2084.470s 56662.913us 1 1 100.00
alert_test 1 1 100.00
sram_ctrl_alert_test 0.830s 17.319us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
sram_ctrl_tl_errors 2.010s 129.381us 1 1 100.00
tl_d_illegal_access 1 1 100.00
sram_ctrl_tl_errors 2.010s 129.381us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
sram_ctrl_csr_hw_reset 0.670s 18.535us 1 1 100.00
sram_ctrl_csr_rw 0.810s 26.011us 1 1 100.00
sram_ctrl_csr_aliasing 0.670s 14.868us 1 1 100.00
sram_ctrl_same_csr_outstanding 0.910s 38.405us 1 1 100.00
tl_d_partial_access 4 4 100.00
sram_ctrl_csr_hw_reset 0.670s 18.535us 1 1 100.00
sram_ctrl_csr_rw 0.810s 26.011us 1 1 100.00
sram_ctrl_csr_aliasing 0.670s 14.868us 1 1 100.00
sram_ctrl_same_csr_outstanding 0.910s 38.405us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
passthru_mem_tl_intg_err 1 1 100.00
sram_ctrl_passthru_mem_tl_intg_err 2.200s 407.817us 1 1 100.00
tl_intg_err 1 2 50.00
sram_ctrl_sec_cm 0.820s 1.627us 0 1 0.00
sram_ctrl_tl_intg_err 1.980s 1061.642us 1 1 100.00
prim_count_check 0 1 0.00
sram_ctrl_sec_cm 0.820s 1.627us 0 1 0.00
sec_cm_bus_integrity 1 1 100.00
sram_ctrl_tl_intg_err 1.980s 1061.642us 1 1 100.00
sec_cm_ctrl_config_regwen 1 1 100.00
sram_ctrl_regwen 371.020s 2719.602us 1 1 100.00
sec_cm_readback_config_regwen 1 1 100.00
sram_ctrl_regwen 371.020s 2719.602us 1 1 100.00
sec_cm_exec_config_regwen 1 1 100.00
sram_ctrl_csr_rw 0.810s 26.011us 1 1 100.00
sec_cm_exec_config_mubi 1 1 100.00
sram_ctrl_executable 40.410s 278.793us 1 1 100.00
sec_cm_exec_intersig_mubi 1 1 100.00
sram_ctrl_executable 40.410s 278.793us 1 1 100.00
sec_cm_lc_hw_debug_en_intersig_mubi 1 1 100.00
sram_ctrl_executable 40.410s 278.793us 1 1 100.00
sec_cm_lc_escalate_en_intersig_mubi 1 1 100.00
sram_ctrl_lc_escalation 7.860s 803.399us 1 1 100.00
sec_cm_prim_ram_ctrl_mubi 1 1 100.00
sram_ctrl_mubi_enc_err 1.180s 38.594us 1 1 100.00
sec_cm_mem_integrity 1 1 100.00
sram_ctrl_passthru_mem_tl_intg_err 2.200s 407.817us 1 1 100.00
sec_cm_mem_readback 1 1 100.00
sram_ctrl_readback_err 1.100s 51.080us 1 1 100.00
sec_cm_mem_scramble 1 1 100.00
sram_ctrl_smoke 9.620s 981.711us 1 1 100.00
sec_cm_addr_scramble 1 1 100.00
sram_ctrl_smoke 9.620s 981.711us 1 1 100.00
sec_cm_instr_bus_lc_gated 1 1 100.00
sram_ctrl_executable 40.410s 278.793us 1 1 100.00
sec_cm_ram_tl_lc_gate_fsm_sparse 0 1 0.00
sram_ctrl_sec_cm 0.820s 1.627us 0 1 0.00
sec_cm_key_global_esc 1 1 100.00
sram_ctrl_lc_escalation 7.860s 803.399us 1 1 100.00
sec_cm_key_local_esc 0 1 0.00
sram_ctrl_sec_cm 0.820s 1.627us 0 1 0.00
sec_cm_init_ctr_redun 0 1 0.00
sram_ctrl_sec_cm 0.820s 1.627us 0 1 0.00
sec_cm_scramble_key_sideload 1 1 100.00
sram_ctrl_smoke 9.620s 981.711us 1 1 100.00
sec_cm_tlul_fifo_ctr_redun 0 1 0.00
sram_ctrl_sec_cm 0.820s 1.627us 0 1 0.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
sram_ctrl_stress_all_with_rand_reset 15.740s 573.489us 1 1 100.00