Simulation Results: uart

 
26/11/2025 16:02:05 sha: 2b9f4df json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 81.23 %
  • code
  • 95.84 %
  • assert
  • 97.12 %
  • func
  • 50.71 %
  • line
  • 99.17 %
  • branch
  • 97.44 %
  • cond
  • 95.22 %
  • toggle
  • 91.55 %
Validation stages
V1
100.00%
V2
97.06%
V2S
100.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
uart_smoke 9.260s 5759.691us 1 1 100.00
csr_hw_reset 1 1 100.00
uart_csr_hw_reset 0.570s 13.024us 1 1 100.00
csr_rw 1 1 100.00
uart_csr_rw 0.580s 13.606us 1 1 100.00
csr_bit_bash 1 1 100.00
uart_csr_bit_bash 1.560s 230.527us 1 1 100.00
csr_aliasing 1 1 100.00
uart_csr_aliasing 0.670s 49.570us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
uart_csr_mem_rw_with_rand_reset 0.790s 435.045us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
uart_csr_rw 0.580s 13.606us 1 1 100.00
uart_csr_aliasing 0.670s 49.570us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
base_random_seq 1 1 100.00
uart_tx_rx 15.120s 113470.313us 1 1 100.00
parity 2 2 100.00
uart_smoke 9.260s 5759.691us 1 1 100.00
uart_tx_rx 15.120s 113470.313us 1 1 100.00
parity_error 2 2 100.00
uart_intr 9.280s 22831.953us 1 1 100.00
uart_rx_parity_err 12.700s 75014.452us 1 1 100.00
watermark 2 2 100.00
uart_tx_rx 15.120s 113470.313us 1 1 100.00
uart_intr 9.280s 22831.953us 1 1 100.00
fifo_full 1 1 100.00
uart_fifo_full 20.740s 22946.136us 1 1 100.00
fifo_overflow 1 1 100.00
uart_fifo_overflow 12.790s 14261.812us 1 1 100.00
fifo_reset 1 1 100.00
uart_fifo_reset 133.430s 127205.450us 1 1 100.00
rx_frame_err 1 1 100.00
uart_intr 9.280s 22831.953us 1 1 100.00
rx_break_err 1 1 100.00
uart_intr 9.280s 22831.953us 1 1 100.00
rx_timeout 1 1 100.00
uart_intr 9.280s 22831.953us 1 1 100.00
perf 1 1 100.00
uart_perf 99.880s 12323.425us 1 1 100.00
sys_loopback 1 1 100.00
uart_loopback 3.400s 5606.865us 1 1 100.00
line_loopback 1 1 100.00
uart_loopback 3.400s 5606.865us 1 1 100.00
rx_noise_filter 0 1 0.00
uart_noise_filter 3.770s 4181.005us 0 1 0.00
rx_start_bit_filter 1 1 100.00
uart_rx_start_bit_filter 1.410s 3417.047us 1 1 100.00
tx_overide 1 1 100.00
uart_tx_ovrd 1.090s 3902.931us 1 1 100.00
rx_oversample 1 1 100.00
uart_rx_oversample 9.350s 6616.734us 1 1 100.00
long_b2b_transfer 1 1 100.00
uart_long_xfer_wo_dly 197.960s 34984.870us 1 1 100.00
stress_all 1 1 100.00
uart_stress_all 304.970s 234505.885us 1 1 100.00
alert_test 1 1 100.00
uart_alert_test 0.530s 35.690us 1 1 100.00
intr_test 1 1 100.00
uart_intr_test 0.570s 14.155us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
uart_tl_errors 1.220s 285.025us 1 1 100.00
tl_d_illegal_access 1 1 100.00
uart_tl_errors 1.220s 285.025us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
uart_csr_hw_reset 0.570s 13.024us 1 1 100.00
uart_csr_rw 0.580s 13.606us 1 1 100.00
uart_csr_aliasing 0.670s 49.570us 1 1 100.00
uart_same_csr_outstanding 0.680s 108.068us 1 1 100.00
tl_d_partial_access 4 4 100.00
uart_csr_hw_reset 0.570s 13.024us 1 1 100.00
uart_csr_rw 0.580s 13.606us 1 1 100.00
uart_csr_aliasing 0.670s 49.570us 1 1 100.00
uart_same_csr_outstanding 0.680s 108.068us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
uart_sec_cm 0.790s 76.038us 1 1 100.00
uart_tl_intg_err 0.940s 92.252us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
uart_tl_intg_err 0.940s 92.252us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
uart_stress_all_with_rand_reset 23.280s 2667.078us 1 1 100.00