| V1 |
|
100.00% |
| V2 |
|
79.17% |
| V2S |
|
88.89% |
| V3 |
|
100.00% |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| smoke | 1 | 1 | 100.00 | |||
| alert_handler_smoke | 4.400s | 73.676us | 1 | 1 | 100.00 | |
| csr_hw_reset | 1 | 1 | 100.00 | |||
| alert_handler_csr_hw_reset | 3.720s | 25.385us | 1 | 1 | 100.00 | |
| csr_rw | 1 | 1 | 100.00 | |||
| alert_handler_csr_rw | 3.390s | 68.208us | 1 | 1 | 100.00 | |
| csr_bit_bash | 1 | 1 | 100.00 | |||
| alert_handler_csr_bit_bash | 172.690s | 1854.644us | 1 | 1 | 100.00 | |
| csr_aliasing | 1 | 1 | 100.00 | |||
| alert_handler_csr_aliasing | 130.640s | 1300.438us | 1 | 1 | 100.00 | |
| csr_mem_rw_with_rand_reset | 1 | 1 | 100.00 | |||
| alert_handler_csr_mem_rw_with_rand_reset | 7.250s | 152.861us | 1 | 1 | 100.00 | |
| regwen_csr_and_corresponding_lockable_csr | 2 | 2 | 100.00 | |||
| alert_handler_csr_rw | 3.390s | 68.208us | 1 | 1 | 100.00 | |
| alert_handler_csr_aliasing | 130.640s | 1300.438us | 1 | 1 | 100.00 | |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| esc_accum | 1 | 1 | 100.00 | |||
| alert_handler_esc_alert_accum | 64.250s | 5435.495us | 1 | 1 | 100.00 | |
| esc_timeout | 1 | 1 | 100.00 | |||
| alert_handler_esc_intr_timeout | 18.110s | 331.561us | 1 | 1 | 100.00 | |
| entropy | 0 | 1 | 0.00 | |||
| alert_handler_entropy | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| sig_int_fail | 1 | 1 | 100.00 | |||
| alert_handler_sig_int_fail | 23.300s | 953.429us | 1 | 1 | 100.00 | |
| clk_skew | 1 | 1 | 100.00 | |||
| alert_handler_smoke | 4.400s | 73.676us | 1 | 1 | 100.00 | |
| random_alerts | 1 | 1 | 100.00 | |||
| alert_handler_random_alerts | 21.460s | 307.728us | 1 | 1 | 100.00 | |
| random_classes | 1 | 1 | 100.00 | |||
| alert_handler_random_classes | 25.260s | 262.098us | 1 | 1 | 100.00 | |
| ping_timeout | 0 | 1 | 0.00 | |||
| alert_handler_ping_timeout | 18.240s | 441.641us | 0 | 1 | 0.00 | |
| lpg | 0 | 2 | 0.00 | |||
| alert_handler_lpg | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| alert_handler_lpg_stub_clk | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| stress_all | 0 | 1 | 0.00 | |||
| alert_handler_stress_all | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| alert_handler_entropy_stress_test | 1 | 1 | 100.00 | |||
| alert_handler_entropy_stress | 33.710s | 892.048us | 1 | 1 | 100.00 | |
| alert_handler_alert_accum_saturation | 1 | 1 | 100.00 | |||
| alert_handler_alert_accum_saturation | 4.560s | 56.115us | 1 | 1 | 100.00 | |
| intr_test | 1 | 1 | 100.00 | |||
| alert_handler_intr_test | 1.430s | 8.129us | 1 | 1 | 100.00 | |
| tl_d_oob_addr_access | 1 | 1 | 100.00 | |||
| alert_handler_tl_errors | 10.010s | 335.804us | 1 | 1 | 100.00 | |
| tl_d_illegal_access | 1 | 1 | 100.00 | |||
| alert_handler_tl_errors | 10.010s | 335.804us | 1 | 1 | 100.00 | |
| tl_d_outstanding_access | 4 | 4 | 100.00 | |||
| alert_handler_csr_hw_reset | 3.720s | 25.385us | 1 | 1 | 100.00 | |
| alert_handler_csr_rw | 3.390s | 68.208us | 1 | 1 | 100.00 | |
| alert_handler_csr_aliasing | 130.640s | 1300.438us | 1 | 1 | 100.00 | |
| alert_handler_same_csr_outstanding | 16.090s | 341.663us | 1 | 1 | 100.00 | |
| tl_d_partial_access | 4 | 4 | 100.00 | |||
| alert_handler_csr_hw_reset | 3.720s | 25.385us | 1 | 1 | 100.00 | |
| alert_handler_csr_rw | 3.390s | 68.208us | 1 | 1 | 100.00 | |
| alert_handler_csr_aliasing | 130.640s | 1300.438us | 1 | 1 | 100.00 | |
| alert_handler_same_csr_outstanding | 16.090s | 341.663us | 1 | 1 | 100.00 | |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| shadow_reg_update_error | 1 | 1 | 100.00 | |||
| alert_handler_shadow_reg_errors | 128.770s | 9135.723us | 1 | 1 | 100.00 | |
| shadow_reg_read_clear_staged_value | 1 | 1 | 100.00 | |||
| alert_handler_shadow_reg_errors | 128.770s | 9135.723us | 1 | 1 | 100.00 | |
| shadow_reg_storage_error | 1 | 1 | 100.00 | |||
| alert_handler_shadow_reg_errors | 128.770s | 9135.723us | 1 | 1 | 100.00 | |
| shadowed_reset_glitch | 1 | 1 | 100.00 | |||
| alert_handler_shadow_reg_errors | 128.770s | 9135.723us | 1 | 1 | 100.00 | |
| shadow_reg_update_error_with_csr_rw | 1 | 1 | 100.00 | |||
| alert_handler_shadow_reg_errors_with_csr_rw | 298.690s | 10393.764us | 1 | 1 | 100.00 | |
| tl_intg_err | 2 | 2 | 100.00 | |||
| alert_handler_sec_cm | 17.080s | 212.810us | 1 | 1 | 100.00 | |
| alert_handler_tl_intg_err | 2.690s | 59.718us | 1 | 1 | 100.00 | |
| sec_cm_bus_integrity | 1 | 1 | 100.00 | |||
| alert_handler_tl_intg_err | 2.690s | 59.718us | 1 | 1 | 100.00 | |
| sec_cm_config_shadow | 1 | 1 | 100.00 | |||
| alert_handler_shadow_reg_errors | 128.770s | 9135.723us | 1 | 1 | 100.00 | |
| sec_cm_ping_timer_config_regwen | 1 | 1 | 100.00 | |||
| alert_handler_smoke | 4.400s | 73.676us | 1 | 1 | 100.00 | |
| sec_cm_alert_config_regwen | 1 | 1 | 100.00 | |||
| alert_handler_smoke | 4.400s | 73.676us | 1 | 1 | 100.00 | |
| sec_cm_alert_loc_config_regwen | 1 | 1 | 100.00 | |||
| alert_handler_smoke | 4.400s | 73.676us | 1 | 1 | 100.00 | |
| sec_cm_class_config_regwen | 1 | 1 | 100.00 | |||
| alert_handler_smoke | 4.400s | 73.676us | 1 | 1 | 100.00 | |
| sec_cm_alert_intersig_diff | 1 | 1 | 100.00 | |||
| alert_handler_sig_int_fail | 23.300s | 953.429us | 1 | 1 | 100.00 | |
| sec_cm_lpg_intersig_mubi | 0 | 1 | 0.00 | |||
| alert_handler_lpg | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| sec_cm_esc_intersig_diff | 1 | 1 | 100.00 | |||
| alert_handler_sig_int_fail | 23.300s | 953.429us | 1 | 1 | 100.00 | |
| sec_cm_alert_rx_intersig_bkgn_chk | 0 | 1 | 0.00 | |||
| alert_handler_entropy | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| sec_cm_esc_tx_intersig_bkgn_chk | 0 | 1 | 0.00 | |||
| alert_handler_entropy | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| sec_cm_esc_timer_fsm_sparse | 1 | 1 | 100.00 | |||
| alert_handler_sec_cm | 17.080s | 212.810us | 1 | 1 | 100.00 | |
| sec_cm_ping_timer_fsm_sparse | 1 | 1 | 100.00 | |||
| alert_handler_sec_cm | 17.080s | 212.810us | 1 | 1 | 100.00 | |
| sec_cm_esc_timer_fsm_local_esc | 1 | 1 | 100.00 | |||
| alert_handler_sec_cm | 17.080s | 212.810us | 1 | 1 | 100.00 | |
| sec_cm_ping_timer_fsm_local_esc | 1 | 1 | 100.00 | |||
| alert_handler_sec_cm | 17.080s | 212.810us | 1 | 1 | 100.00 | |
| sec_cm_esc_timer_fsm_global_esc | 1 | 1 | 100.00 | |||
| alert_handler_sec_cm | 17.080s | 212.810us | 1 | 1 | 100.00 | |
| sec_cm_accu_ctr_redun | 1 | 1 | 100.00 | |||
| alert_handler_sec_cm | 17.080s | 212.810us | 1 | 1 | 100.00 | |
| sec_cm_esc_timer_ctr_redun | 1 | 1 | 100.00 | |||
| alert_handler_sec_cm | 17.080s | 212.810us | 1 | 1 | 100.00 | |
| sec_cm_ping_timer_ctr_redun | 1 | 1 | 100.00 | |||
| alert_handler_sec_cm | 17.080s | 212.810us | 1 | 1 | 100.00 | |
| sec_cm_ping_timer_lfsr_redun | 1 | 1 | 100.00 | |||
| alert_handler_sec_cm | 17.080s | 212.810us | 1 | 1 | 100.00 | |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| stress_all_with_rand_reset | 1 | 1 | 100.00 | |||
| alert_handler_stress_all_with_rand_reset | 329.840s | 8710.163us | 1 | 1 | 100.00 | |