Simulation Results: chip

 
27/11/2025 16:08:38 sha: 8a15de8 json Branch: master Tool: vcs [unknown]
Coverage statistics
Validation stages
V1
0.00%
V2
0.00%
V2S
0.00%
V3
0.00%
unmapped
0.00%
Testpoint Test Max Runtime Sim Time Pass Total %
chip_sw_uart_tx_rx 0 1 0.00
chip_sw_uart_tx_rx 0.000s 0.000us 0 1 0.00
chip_sw_uart_rx_overflow 0 1 0.00
chip_sw_uart_tx_rx 0.000s 0.000us 0 1 0.00
chip_sw_uart_rand_baudrate 0 1 0.00
chip_sw_uart_rand_baudrate 0.000s 0.000us 0 1 0.00
chip_sw_uart_tx_rx_alt_clk_freq 0 1 0.00
chip_sw_uart_tx_rx_alt_clk_freq 0.000s 0.000us 0 1 0.00
chip_sw_gpio_out 0 1 0.00
chip_sw_gpio 0.000s 0.000us 0 1 0.00
chip_sw_gpio_in 0 1 0.00
chip_sw_gpio 0.000s 0.000us 0 1 0.00
chip_sw_gpio_irq 0 1 0.00
chip_sw_gpio 0.000s 0.000us 0 1 0.00
chip_sw_example_tests 0 4 0.00
chip_sw_example_rom 0.000s 0.000us 0 1 0.00
chip_sw_example_manufacturer 0.000s 0.000us 0 1 0.00
chip_sw_example_concurrency 0.000s 0.000us 0 1 0.00
chip_sw_uart_smoketest_signed 0.000s 0.000us 0 1 0.00
csr_bit_bash 0 1 0.00
chip_csr_bit_bash 0.000s 0.000us 0 1 0.00
csr_aliasing 0 1 0.00
chip_csr_aliasing 0.000s 0.000us 0 1 0.00
regwen_csr_and_corresponding_lockable_csr 0 1 0.00
chip_csr_aliasing 0.000s 0.000us 0 1 0.00
xbar_smoke 0 1 0.00
xbar_smoke 0.000s 0.000us 0 1 0.00
Testpoint Test Max Runtime Sim Time Pass Total %
chip_sw_spi_device_flash_mode 0 1 0.00
chip_sw_uart_tx_rx_bootstrap 0.000s 0.000us 0 1 0.00
chip_sw_spi_device_pass_through 0 1 0.00
chip_sw_spi_device_pass_through 0.000s 0.000us 0 1 0.00
chip_sw_spi_device_pass_through_collision 0 1 0.00
chip_sw_spi_device_pass_through_collision 0.000s 0.000us 0 1 0.00
chip_sw_spi_device_tpm 0 1 0.00
chip_sw_spi_device_tpm 0.000s 0.000us 0 1 0.00
chip_sw_spi_host_tx_rx 0 1 0.00
chip_sw_spi_host_tx_rx 0.000s 0.000us 0 1 0.00
chip_sw_i2c_host_tx_rx 0 1 0.00
chip_sw_i2c_host_tx_rx 0.000s 0.000us 0 1 0.00
chip_sw_i2c_device_tx_rx 0 1 0.00
chip_sw_i2c_device_tx_rx 0.000s 0.000us 0 1 0.00
chip_pin_mux 0 1 0.00
chip_padctrl_attributes 0.000s 0.000us 0 1 0.00
chip_padctrl_attributes 0 1 0.00
chip_padctrl_attributes 0.000s 0.000us 0 1 0.00
chip_sw_sleep_pin_wake 0 1 0.00
chip_sw_sleep_pin_wake 0.000s 0.000us 0 1 0.00
chip_sw_sleep_pin_retention 0 1 0.00
chip_sw_sleep_pin_retention 0.000s 0.000us 0 1 0.00
chip_sw_data_integrity 0 1 0.00
chip_sw_data_integrity_escalation 0.000s 0.000us 0 1 0.00
chip_sw_instruction_integrity 0 1 0.00
chip_sw_data_integrity_escalation 0.000s 0.000us 0 1 0.00
chip_jtag_csr_rw 0 1 0.00
chip_jtag_csr_rw 0.000s 0.000us 0 1 0.00
chip_jtag_mem_access 0 1 0.00
chip_jtag_mem_access 0.000s 0.000us 0 1 0.00
chip_rv_dm_ndm_reset_req 0 1 0.00
chip_rv_dm_ndm_reset_req 0.000s 0.000us 0 1 0.00
chip_sw_rv_dm_ndm_reset_req_when_cpu_halted 0 1 0.00
chip_sw_rv_dm_ndm_reset_req_when_cpu_halted 0.000s 0.000us 0 1 0.00
chip_rv_dm_access_after_wakeup 0 1 0.00
chip_sw_rv_dm_access_after_wakeup 0.000s 0.000us 0 1 0.00
chip_rv_dm_lc_disabled 0 1 0.00
chip_rv_dm_lc_disabled 0.000s 0.000us 0 1 0.00
chip_sw_timer 0 1 0.00
chip_sw_rv_timer_irq 0.000s 0.000us 0 1 0.00
chip_sw_aon_timer_wakeup_irq 0 1 0.00
chip_sw_aon_timer_irq 0.000s 0.000us 0 1 0.00
chip_sw_aon_timer_wdog_bark_irq 0 1 0.00
chip_sw_aon_timer_irq 0.000s 0.000us 0 1 0.00
chip_sw_aon_timer_wdog_lc_escalate 0 1 0.00
chip_sw_aon_timer_wdog_lc_escalate 0.000s 0.000us 0 1 0.00
chip_sw_aon_timer_wdog_bite_reset 0 1 0.00
chip_sw_aon_timer_wdog_bite_reset 0.000s 0.000us 0 1 0.00
chip_sw_aon_timer_sleep_wdog_bite_reset 0 1 0.00
chip_sw_aon_timer_wdog_bite_reset 0.000s 0.000us 0 1 0.00
chip_sw_aon_timer_sleep_wdog_sleep_pause 0 1 0.00
chip_sw_aon_timer_sleep_wdog_sleep_pause 0.000s 0.000us 0 1 0.00
chip_sw_plic_sw_irq 0 1 0.00
chip_sw_plic_sw_irq 0.000s 0.000us 0 1 0.00
chip_sw_clkmgr_idle_trans 0 4 0.00
chip_sw_otbn_randomness 0.000s 0.000us 0 1 0.00
chip_sw_aes_idle 0.000s 0.000us 0 1 0.00
chip_sw_hmac_enc_idle 0.000s 0.000us 0 1 0.00
chip_sw_kmac_idle 0.000s 0.000us 0 1 0.00
chip_sw_clkmgr_off_trans 0 4 0.00
chip_sw_clkmgr_off_aes_trans 0.000s 0.000us 0 1 0.00
chip_sw_clkmgr_off_hmac_trans 0.000s 0.000us 0 1 0.00
chip_sw_clkmgr_off_kmac_trans 0.000s 0.000us 0 1 0.00
chip_sw_clkmgr_off_otbn_trans 0.000s 0.000us 0 1 0.00
chip_sw_clkmgr_jitter 0 7 0.00
chip_sw_otbn_ecdsa_op_irq_jitter_en 0.000s 0.000us 0 1 0.00
chip_sw_aes_enc_jitter_en 0.000s 0.000us 0 1 0.00
chip_sw_hmac_enc_jitter_en 0.000s 0.000us 0 1 0.00
chip_sw_keymgr_dpe_key_derivation_jitter_en 0.000s 0.000us 0 1 0.00
chip_sw_kmac_mode_kmac_jitter_en 0.000s 0.000us 0 1 0.00
chip_sw_sram_ctrl_scrambled_access_jitter_en 0.000s 0.000us 0 1 0.00
chip_sw_clkmgr_jitter 0.000s 0.000us 0 1 0.00
chip_sw_clkmgr_extended_range 0 8 0.00
chip_sw_clkmgr_jitter_reduced_freq 0.000s 0.000us 0 1 0.00
chip_sw_otbn_ecdsa_op_irq_jitter_en_reduced_freq 0.000s 0.000us 0 1 0.00
chip_sw_aes_enc_jitter_en_reduced_freq 0.000s 0.000us 0 1 0.00
chip_sw_hmac_enc_jitter_en_reduced_freq 0.000s 0.000us 0 1 0.00
chip_sw_keymgr_dpe_key_derivation_jitter_en_reduced_freq 0.000s 0.000us 0 1 0.00
chip_sw_kmac_mode_kmac_jitter_en_reduced_freq 0.000s 0.000us 0 1 0.00
chip_sw_sram_ctrl_scrambled_access_jitter_en_reduced_freq 0.000s 0.000us 0 1 0.00
chip_sw_csrng_edn_concurrency_reduced_freq 0.000s 0.000us 0 1 0.00
chip_sw_clkmgr_deep_sleep_frequency 0 1 0.00
chip_sw_ast_clk_outputs 0.000s 0.000us 0 1 0.00
chip_sw_clkmgr_sleep_frequency 0 1 0.00
chip_sw_clkmgr_sleep_frequency 0.000s 0.000us 0 1 0.00
chip_sw_clkmgr_reset_frequency 0 1 0.00
chip_sw_clkmgr_reset_frequency 0.000s 0.000us 0 1 0.00
chip_sw_clkmgr_escalation_reset 0 1 0.00
chip_sw_all_escalation_resets 0.000s 0.000us 0 1 0.00
chip_sw_pwrmgr_external_full_reset 0 1 0.00
chip_sw_pwrmgr_full_aon_reset 0.000s 0.000us 0 1 0.00
chip_sw_pwrmgr_sleep_all_reset_reqs 0 1 0.00
chip_sw_aon_timer_wdog_bite_reset 0.000s 0.000us 0 1 0.00
chip_sw_pwrmgr_wdog_reset 0 1 0.00
chip_sw_pwrmgr_wdog_reset 0.000s 0.000us 0 1 0.00
chip_sw_pwrmgr_aon_power_glitch_reset 0 1 0.00
chip_sw_pwrmgr_full_aon_reset 0.000s 0.000us 0 1 0.00
chip_sw_pwrmgr_main_power_glitch_reset 0 1 0.00
chip_sw_pwrmgr_main_power_glitch_reset 0.000s 0.000us 0 1 0.00
chip_sw_pwrmgr_random_sleep_power_glitch_reset 0 1 0.00
chip_sw_pwrmgr_random_sleep_power_glitch_reset 0.000s 0.000us 0 1 0.00
chip_sw_pwrmgr_deep_sleep_power_glitch_reset 0 1 0.00
chip_sw_pwrmgr_deep_sleep_power_glitch_reset 0.000s 0.000us 0 1 0.00
chip_sw_pwrmgr_sleep_power_glitch_reset 0 1 0.00
chip_sw_pwrmgr_sleep_power_glitch_reset 0.000s 0.000us 0 1 0.00
chip_sw_pwrmgr_sleep_disabled 0 1 0.00
chip_sw_pwrmgr_sleep_disabled 0.000s 0.000us 0 1 0.00
chip_sw_pwrmgr_escalation_reset 0 1 0.00
chip_sw_all_escalation_resets 0.000s 0.000us 0 1 0.00
chip_sw_rstmgr_sys_reset_info 0 1 0.00
chip_rv_dm_ndm_reset_req 0.000s 0.000us 0 1 0.00
chip_sw_rstmgr_cpu_info 0 1 0.00
chip_sw_rstmgr_cpu_info 0.000s 0.000us 0 1 0.00
chip_sw_rstmgr_sw_req_reset 0 1 0.00
chip_sw_rstmgr_sw_req 0.000s 0.000us 0 1 0.00
chip_sw_rstmgr_alert_info 0 1 0.00
chip_sw_rstmgr_alert_info 0.000s 0.000us 0 1 0.00
chip_sw_rstmgr_sw_rst 0 1 0.00
chip_sw_rstmgr_sw_rst 0.000s 0.000us 0 1 0.00
chip_sw_rstmgr_escalation_reset 0 1 0.00
chip_sw_all_escalation_resets 0.000s 0.000us 0 1 0.00
chip_sw_alert_handler_alerts 0 1 0.00
chip_sw_alert_test 0.000s 0.000us 0 1 0.00
chip_sw_alert_handler_escalations 0 1 0.00
chip_sw_alert_handler_escalation 0.000s 0.000us 0 1 0.00
chip_sw_all_escalation_resets 0 1 0.00
chip_sw_all_escalation_resets 0.000s 0.000us 0 1 0.00
chip_sw_alert_handler_entropy 0 1 0.00
chip_sw_alert_handler_entropy 0.000s 0.000us 0 1 0.00
chip_sw_alert_handler_crashdump 0 1 0.00
chip_sw_rstmgr_alert_info 0.000s 0.000us 0 1 0.00
chip_sw_alert_handler_ping_timeout 0 1 0.00
chip_sw_alert_handler_ping_timeout 0.000s 0.000us 0 1 0.00
chip_sw_alert_handler_lpg_sleep_mode_alerts 0 1 0.00
chip_sw_alert_handler_lpg_sleep_mode_alerts 0.000s 0.000us 0 1 0.00
chip_sw_alert_handler_lpg_sleep_mode_pings 0 1 0.00
chip_sw_alert_handler_lpg_sleep_mode_pings 0.000s 0.000us 0 1 0.00
chip_sw_alert_handler_lpg_clock_off 0 1 0.00
chip_sw_alert_handler_lpg_clkoff 0.000s 0.000us 0 1 0.00
chip_sw_alert_handler_lpg_reset_toggle 0 1 0.00
chip_sw_alert_handler_lpg_reset_toggle 0.000s 0.000us 0 1 0.00
chip_sw_alert_handler_reverse_ping_in_deep_sleep 0 1 0.00
chip_sw_alert_handler_reverse_ping_in_deep_sleep 0.000s 0.000us 0 1 0.00
chip_sw_lc_ctrl_alert_handler_escalation 0 1 0.00
chip_sw_alert_handler_escalation 0.000s 0.000us 0 1 0.00
chip_sw_lc_ctrl_jtag_access 0 1 0.00
chip_sw_lc_ctrl_transition 0.000s 0.000us 0 1 0.00
chip_sw_lc_ctrl_otp_hw_cfg 0 1 0.00
chip_sw_lc_ctrl_otp_hw_cfg 0.000s 0.000us 0 1 0.00
chip_sw_lc_ctrl_init 0 1 0.00
chip_sw_lc_ctrl_transition 0.000s 0.000us 0 1 0.00
chip_sw_lc_ctrl_transitions 0 1 0.00
chip_sw_lc_ctrl_transition 0.000s 0.000us 0 1 0.00
chip_sw_lc_ctrl_kmac_req 0 1 0.00
chip_sw_lc_ctrl_transition 0.000s 0.000us 0 1 0.00
chip_sw_lc_ctrl_key_div 0 1 0.00
chip_sw_keymgr_dpe_key_derivation_prod 0.000s 0.000us 0 1 0.00
chip_sw_lc_ctrl_broadcast 0 10 0.00
chip_prim_tl_access 0.000s 0.000us 0 1 0.00
chip_rv_dm_lc_disabled 0.000s 0.000us 0 1 0.00
chip_sw_otp_ctrl_lc_signals_test_unlocked0 0.000s 0.000us 0 1 0.00
chip_sw_otp_ctrl_lc_signals_dev 0.000s 0.000us 0 1 0.00
chip_sw_otp_ctrl_lc_signals_prod 0.000s 0.000us 0 1 0.00
chip_sw_otp_ctrl_lc_signals_rma 0.000s 0.000us 0 1 0.00
chip_sw_lc_ctrl_transition 0.000s 0.000us 0 1 0.00
chip_sw_keymgr_dpe_key_derivation 0.000s 0.000us 0 1 0.00
chip_sw_rom_ctrl_integrity_check 0.000s 0.000us 0 1 0.00
chip_sw_sram_ctrl_execution_main 0.000s 0.000us 0 1 0.00
chip_sw_aes_enc 0 2 0.00
chip_sw_aes_enc 0.000s 0.000us 0 1 0.00
chip_sw_aes_enc_jitter_en 0.000s 0.000us 0 1 0.00
chip_sw_aes_entropy 0 1 0.00
chip_sw_aes_entropy 0.000s 0.000us 0 1 0.00
chip_sw_aes_idle 0 1 0.00
chip_sw_aes_idle 0.000s 0.000us 0 1 0.00
chip_sw_hmac_enc 0 2 0.00
chip_sw_hmac_enc 0.000s 0.000us 0 1 0.00
chip_sw_hmac_enc_jitter_en 0.000s 0.000us 0 1 0.00
chip_sw_hmac_idle 0 1 0.00
chip_sw_hmac_enc_idle 0.000s 0.000us 0 1 0.00
chip_sw_kmac_enc 0 3 0.00
chip_sw_kmac_mode_cshake 0.000s 0.000us 0 1 0.00
chip_sw_kmac_mode_kmac 0.000s 0.000us 0 1 0.00
chip_sw_kmac_mode_kmac_jitter_en 0.000s 0.000us 0 1 0.00
chip_sw_kmac_app_keymgr 0 1 0.00
chip_sw_keymgr_dpe_key_derivation 0.000s 0.000us 0 1 0.00
chip_sw_kmac_app_lc 0 1 0.00
chip_sw_lc_ctrl_transition 0.000s 0.000us 0 1 0.00
chip_sw_kmac_app_rom 0 1 0.00
chip_sw_kmac_app_rom 0.000s 0.000us 0 1 0.00
chip_sw_kmac_entropy 0 1 0.00
chip_sw_kmac_entropy 0.000s 0.000us 0 1 0.00
chip_sw_kmac_idle 0 1 0.00
chip_sw_kmac_idle 0.000s 0.000us 0 1 0.00
chip_sw_entropy_src_csrng 0 1 0.00
chip_sw_entropy_src_csrng 0.000s 0.000us 0 1 0.00
chip_sw_csrng_edn_cmd 0 1 0.00
chip_sw_entropy_src_csrng 0.000s 0.000us 0 1 0.00
chip_sw_csrng_fuse_en_sw_app_read 0 1 0.00
chip_sw_csrng_fuse_en_sw_app_read_test 0.000s 0.000us 0 1 0.00
chip_sw_csrng_known_answer_tests 0 1 0.00
chip_sw_csrng_kat_test 0.000s 0.000us 0 1 0.00
chip_sw_edn_entropy_reqs 0 1 0.00
chip_sw_csrng_edn_concurrency 0.000s 0.000us 0 1 0.00
chip_sw_keymgr_dpe_key_derivation 0 2 0.00
chip_sw_keymgr_dpe_key_derivation 0.000s 0.000us 0 1 0.00
chip_sw_keymgr_dpe_key_derivation_jitter_en 0.000s 0.000us 0 1 0.00
chip_sw_otbn_op 0 2 0.00
chip_sw_otbn_ecdsa_op_irq 0.000s 0.000us 0 1 0.00
chip_sw_otbn_ecdsa_op_irq_jitter_en 0.000s 0.000us 0 1 0.00
chip_sw_otbn_rnd_entropy 0 1 0.00
chip_sw_otbn_randomness 0.000s 0.000us 0 1 0.00
chip_sw_otbn_urnd_entropy 0 1 0.00
chip_sw_otbn_randomness 0.000s 0.000us 0 1 0.00
chip_sw_otbn_idle 0 1 0.00
chip_sw_otbn_randomness 0.000s 0.000us 0 1 0.00
chip_sw_otbn_mem_scramble 0 1 0.00
chip_sw_otbn_mem_scramble 0.000s 0.000us 0 1 0.00
chip_sw_rom_access 0 1 0.00
chip_sw_rom_ctrl_integrity_check 0.000s 0.000us 0 1 0.00
chip_sw_rom_ctrl_integrity_check 0 1 0.00
chip_sw_rom_ctrl_integrity_check 0.000s 0.000us 0 1 0.00
chip_sw_sram_scrambled_access 0 2 0.00
chip_sw_sram_ctrl_scrambled_access 0.000s 0.000us 0 1 0.00
chip_sw_sram_ctrl_scrambled_access_jitter_en 0.000s 0.000us 0 1 0.00
chip_sw_sram_execution 0 1 0.00
chip_sw_sram_ctrl_execution_main 0.000s 0.000us 0 1 0.00
chip_sw_sram_lc_escalation 0 2 0.00
chip_sw_all_escalation_resets 0.000s 0.000us 0 1 0.00
chip_sw_data_integrity_escalation 0.000s 0.000us 0 1 0.00
chip_otp_ctrl_init 0 1 0.00
chip_sw_lc_ctrl_transition 0.000s 0.000us 0 1 0.00
chip_sw_otp_ctrl_keys 0 4 0.00
chip_sw_otbn_mem_scramble 0.000s 0.000us 0 1 0.00
chip_sw_keymgr_dpe_key_derivation 0.000s 0.000us 0 1 0.00
chip_sw_sram_ctrl_scrambled_access 0.000s 0.000us 0 1 0.00
chip_sw_rv_core_ibex_icache_invalidate 0.000s 0.000us 0 1 0.00
chip_sw_otp_ctrl_entropy 0 4 0.00
chip_sw_otbn_mem_scramble 0.000s 0.000us 0 1 0.00
chip_sw_keymgr_dpe_key_derivation 0.000s 0.000us 0 1 0.00
chip_sw_sram_ctrl_scrambled_access 0.000s 0.000us 0 1 0.00
chip_sw_rv_core_ibex_icache_invalidate 0.000s 0.000us 0 1 0.00
chip_sw_otp_ctrl_program 0 1 0.00
chip_sw_lc_ctrl_transition 0.000s 0.000us 0 1 0.00
chip_sw_otp_ctrl_program_error 0 1 0.00
chip_sw_lc_ctrl_program_error 0.000s 0.000us 0 1 0.00
chip_sw_otp_ctrl_hw_cfg 0 1 0.00
chip_sw_lc_ctrl_otp_hw_cfg 0.000s 0.000us 0 1 0.00
chip_sw_otp_ctrl_lc_signals 0 6 0.00
chip_prim_tl_access 0.000s 0.000us 0 1 0.00
chip_sw_otp_ctrl_lc_signals_test_unlocked0 0.000s 0.000us 0 1 0.00
chip_sw_otp_ctrl_lc_signals_dev 0.000s 0.000us 0 1 0.00
chip_sw_otp_ctrl_lc_signals_prod 0.000s 0.000us 0 1 0.00
chip_sw_otp_ctrl_lc_signals_rma 0.000s 0.000us 0 1 0.00
chip_sw_lc_ctrl_transition 0.000s 0.000us 0 1 0.00
chip_sw_otp_prim_tl_access 0 1 0.00
chip_prim_tl_access 0.000s 0.000us 0 1 0.00
chip_sw_otp_ctrl_nvm_cnt 0 1 0.00
chip_sw_otp_ctrl_nvm_cnt 0.000s 0.000us 0 1 0.00
chip_sw_otp_ctrl_sw_parts 0 1 0.00
chip_sw_otp_ctrl_sw_parts 0.000s 0.000us 0 1 0.00
chip_sw_ast_clk_outputs 0 1 0.00
chip_sw_ast_clk_outputs 0.000s 0.000us 0 1 0.00
chip_sw_ast_sys_clk_jitter 0 7 0.00
chip_sw_otbn_ecdsa_op_irq_jitter_en 0.000s 0.000us 0 1 0.00
chip_sw_aes_enc_jitter_en 0.000s 0.000us 0 1 0.00
chip_sw_hmac_enc_jitter_en 0.000s 0.000us 0 1 0.00
chip_sw_keymgr_dpe_key_derivation_jitter_en 0.000s 0.000us 0 1 0.00
chip_sw_kmac_mode_kmac_jitter_en 0.000s 0.000us 0 1 0.00
chip_sw_sram_ctrl_scrambled_access_jitter_en 0.000s 0.000us 0 1 0.00
chip_sw_clkmgr_jitter 0.000s 0.000us 0 1 0.00
chip_sw_soc_proxy_external_reset_requests 0 1 0.00
chip_sw_soc_proxy_smoketest 0.000s 0.000us 0 1 0.00
chip_sw_soc_proxy_external_irqs 0 1 0.00
chip_sw_soc_proxy_smoketest 0.000s 0.000us 0 1 0.00
chip_sw_soc_proxy_external_wakeup_requests 0 1 0.00
chip_sw_soc_proxy_external_wakeup 0.000s 0.000us 0 1 0.00
chip_sw_soc_proxy_gpios 0 1 0.00
chip_sw_soc_proxy_gpios 0.000s 0.000us 0 1 0.00
chip_sw_nmi_irq 0 1 0.00
chip_sw_rv_core_ibex_nmi_irq 0.000s 0.000us 0 1 0.00
chip_sw_rv_core_ibex_rnd 0 1 0.00
chip_sw_rv_core_ibex_rnd 0.000s 0.000us 0 1 0.00
chip_sw_rv_core_ibex_address_translation 0 1 0.00
chip_sw_rv_core_ibex_address_translation 0.000s 0.000us 0 1 0.00
chip_sw_rv_core_ibex_icache_scrambled_access 0 1 0.00
chip_sw_rv_core_ibex_icache_invalidate 0.000s 0.000us 0 1 0.00
chip_sw_rv_core_ibex_fault_dump 0 1 0.00
chip_sw_rstmgr_cpu_info 0.000s 0.000us 0 1 0.00
chip_sw_rv_core_ibex_double_fault 0 1 0.00
chip_sw_rstmgr_cpu_info 0.000s 0.000us 0 1 0.00
chip_sw_smoketest 0 14 0.00
chip_sw_aes_smoketest 0.000s 0.000us 0 1 0.00
chip_sw_aon_timer_smoketest 0.000s 0.000us 0 1 0.00
chip_sw_clkmgr_smoketest 0.000s 0.000us 0 1 0.00
chip_sw_csrng_smoketest 0.000s 0.000us 0 1 0.00
chip_sw_gpio_smoketest 0.000s 0.000us 0 1 0.00
chip_sw_hmac_smoketest 0.000s 0.000us 0 1 0.00
chip_sw_kmac_smoketest 0.000s 0.000us 0 1 0.00
chip_sw_otbn_smoketest 0.000s 0.000us 0 1 0.00
chip_sw_otp_ctrl_smoketest 0.000s 0.000us 0 1 0.00
chip_sw_rv_plic_smoketest 0.000s 0.000us 0 1 0.00
chip_sw_rv_timer_smoketest 0.000s 0.000us 0 1 0.00
chip_sw_rstmgr_smoketest 0.000s 0.000us 0 1 0.00
chip_sw_sram_ctrl_smoketest 0.000s 0.000us 0 1 0.00
chip_sw_uart_smoketest 0.000s 0.000us 0 1 0.00
chip_sw_rom_functests 0 1 0.00
rom_keymgr_functest 0.000s 0.000us 0 1 0.00
chip_sw_signed 0 1 0.00
chip_sw_uart_smoketest_signed 0.000s 0.000us 0 1 0.00
chip_sw_boot 0 1 0.00
chip_sw_uart_tx_rx_bootstrap 0.000s 0.000us 0 1 0.00
chip_sw_secure_boot 0 1 0.00
base_rom_e2e_smoke 0.000s 0.000us 0 1 0.00
chip_lc_scrap 0 4 0.00
chip_sw_lc_ctrl_rma_to_scrap 0.000s 0.000us 0 1 0.00
chip_sw_lc_ctrl_raw_to_scrap 0.000s 0.000us 0 1 0.00
chip_sw_lc_ctrl_test_locked0_to_scrap 0.000s 0.000us 0 1 0.00
chip_sw_lc_ctrl_rand_to_scrap 0.000s 0.000us 0 1 0.00
chip_lc_test_locked 0 2 0.00
chip_rv_dm_lc_disabled 0.000s 0.000us 0 1 0.00
chip_sw_lc_walkthrough_testunlocks 0.000s 0.000us 0 1 0.00
chip_sw_lc_walkthrough 0 5 0.00
chip_sw_lc_walkthrough_dev 0.000s 0.000us 0 1 0.00
chip_sw_lc_walkthrough_prod 0.000s 0.000us 0 1 0.00
chip_sw_lc_walkthrough_prodend 0.000s 0.000us 0 1 0.00
chip_sw_lc_walkthrough_rma 0.000s 0.000us 0 1 0.00
chip_sw_lc_walkthrough_testunlocks 0.000s 0.000us 0 1 0.00
chip_sw_lc_ctrl_volatile_raw_unlock 0 3 0.00
chip_sw_lc_ctrl_volatile_raw_unlock 0.000s 0.000us 0 1 0.00
chip_sw_lc_ctrl_volatile_raw_unlock_ext_clk_48mhz 0.000s 0.000us 0 1 0.00
rom_volatile_raw_unlock 0.000s 0.000us 0 1 0.00
chip_sw_rom_raw_unlock 0 1 0.00
rom_raw_unlock 0.000s 0.000us 0 1 0.00
chip_sw_exit_test_unlocked_bootstrap 0 1 0.00
chip_sw_exit_test_unlocked_bootstrap 0.000s 0.000us 0 1 0.00
chip_sw_inject_scramble_seed 0 1 0.00
chip_sw_inject_scramble_seed 0.000s 0.000us 0 1 0.00
tl_d_oob_addr_access 0 1 0.00
chip_tl_errors 0.000s 0.000us 0 1 0.00
tl_d_illegal_access 0 1 0.00
chip_tl_errors 0.000s 0.000us 0 1 0.00
tl_d_outstanding_access 0 2 0.00
chip_csr_aliasing 0.000s 0.000us 0 1 0.00
chip_same_csr_outstanding 0.000s 0.000us 0 1 0.00
tl_d_partial_access 0 2 0.00
chip_csr_aliasing 0.000s 0.000us 0 1 0.00
chip_same_csr_outstanding 0.000s 0.000us 0 1 0.00
xbar_base_random_sequence 0 1 0.00
xbar_random 0.000s 0.000us 0 1 0.00
xbar_random_delay 0 6 0.00
xbar_smoke_zero_delays 0.000s 0.000us 0 1 0.00
xbar_smoke_large_delays 0.000s 0.000us 0 1 0.00
xbar_smoke_slow_rsp 0.000s 0.000us 0 1 0.00
xbar_random_zero_delays 0.000s 0.000us 0 1 0.00
xbar_random_large_delays 0.000s 0.000us 0 1 0.00
xbar_random_slow_rsp 0.000s 0.000us 0 1 0.00
xbar_unmapped_address 0 2 0.00
xbar_unmapped_addr 0.000s 0.000us 0 1 0.00
xbar_error_and_unmapped_addr 0.000s 0.000us 0 1 0.00
xbar_error_cases 0 2 0.00
xbar_error_random 0.000s 0.000us 0 1 0.00
xbar_error_and_unmapped_addr 0.000s 0.000us 0 1 0.00
xbar_all_access_same_device 0 2 0.00
xbar_access_same_device 0.000s 0.000us 0 1 0.00
xbar_access_same_device_slow_rsp 0.000s 0.000us 0 1 0.00
xbar_all_hosts_use_same_source_id 0 1 0.00
xbar_same_source 0.000s 0.000us 0 1 0.00
xbar_stress_all 0 2 0.00
xbar_stress_all 0.000s 0.000us 0 1 0.00
xbar_stress_all_with_error 0.000s 0.000us 0 1 0.00
xbar_stress_with_reset 0 2 0.00
xbar_stress_all_with_rand_reset 0.000s 0.000us 0 1 0.00
xbar_stress_all_with_reset_error 0.000s 0.000us 0 1 0.00
rom_e2e_smoke 0 1 0.00
rom_e2e_smoke 0.000s 0.000us 0 1 0.00
rom_e2e_shutdown_output 0 1 0.00
rom_e2e_shutdown_output 0.000s 0.000us 0 1 0.00
rom_e2e_shutdown_exception_c 0 1 0.00
rom_e2e_shutdown_exception_c 0.000s 0.000us 0 1 0.00
rom_e2e_boot_policy_valid 0 15 0.00
rom_e2e_boot_policy_valid_a_good_b_good_test_unlocked0 0.000s 0.000us 0 1 0.00
rom_e2e_boot_policy_valid_a_good_b_good_dev 0.000s 0.000us 0 1 0.00
rom_e2e_boot_policy_valid_a_good_b_good_prod 0.000s 0.000us 0 1 0.00
rom_e2e_boot_policy_valid_a_good_b_good_prod_end 0.000s 0.000us 0 1 0.00
rom_e2e_boot_policy_valid_a_good_b_good_rma 0.000s 0.000us 0 1 0.00
rom_e2e_boot_policy_valid_a_good_b_bad_test_unlocked0 0.000s 0.000us 0 1 0.00
rom_e2e_boot_policy_valid_a_good_b_bad_dev 0.000s 0.000us 0 1 0.00
rom_e2e_boot_policy_valid_a_good_b_bad_prod 0.000s 0.000us 0 1 0.00
rom_e2e_boot_policy_valid_a_good_b_bad_prod_end 0.000s 0.000us 0 1 0.00
rom_e2e_boot_policy_valid_a_good_b_bad_rma 0.000s 0.000us 0 1 0.00
rom_e2e_boot_policy_valid_a_bad_b_good_test_unlocked0 0.000s 0.000us 0 1 0.00
rom_e2e_boot_policy_valid_a_bad_b_good_dev 0.000s 0.000us 0 1 0.00
rom_e2e_boot_policy_valid_a_bad_b_good_prod 0.000s 0.000us 0 1 0.00
rom_e2e_boot_policy_valid_a_bad_b_good_prod_end 0.000s 0.000us 0 1 0.00
rom_e2e_boot_policy_valid_a_bad_b_good_rma 0.000s 0.000us 0 1 0.00
rom_e2e_sigverify_always 0 15 0.00
rom_e2e_sigverify_always_a_bad_b_bad_test_unlocked0 0.000s 0.000us 0 1 0.00
rom_e2e_sigverify_always_a_bad_b_bad_dev 0.000s 0.000us 0 1 0.00
rom_e2e_sigverify_always_a_bad_b_bad_prod 0.000s 0.000us 0 1 0.00
rom_e2e_sigverify_always_a_bad_b_bad_prod_end 0.000s 0.000us 0 1 0.00
rom_e2e_sigverify_always_a_bad_b_bad_rma 0.000s 0.000us 0 1 0.00
rom_e2e_sigverify_always_a_bad_b_nothing_test_unlocked0 0.000s 0.000us 0 1 0.00
rom_e2e_sigverify_always_a_bad_b_nothing_dev 0.000s 0.000us 0 1 0.00
rom_e2e_sigverify_always_a_bad_b_nothing_prod 0.000s 0.000us 0 1 0.00
rom_e2e_sigverify_always_a_bad_b_nothing_prod_end 0.000s 0.000us 0 1 0.00
rom_e2e_sigverify_always_a_bad_b_nothing_rma 0.000s 0.000us 0 1 0.00
rom_e2e_sigverify_always_a_nothing_b_bad_test_unlocked0 0.000s 0.000us 0 1 0.00
rom_e2e_sigverify_always_a_nothing_b_bad_dev 0.000s 0.000us 0 1 0.00
rom_e2e_sigverify_always_a_nothing_b_bad_prod 0.000s 0.000us 0 1 0.00
rom_e2e_sigverify_always_a_nothing_b_bad_prod_end 0.000s 0.000us 0 1 0.00
rom_e2e_sigverify_always_a_nothing_b_bad_rma 0.000s 0.000us 0 1 0.00
rom_e2e_asm_init 0 5 0.00
rom_e2e_asm_init_test_unlocked0 0.000s 0.000us 0 1 0.00
rom_e2e_asm_init_dev 0.000s 0.000us 0 1 0.00
rom_e2e_asm_init_prod 0.000s 0.000us 0 1 0.00
rom_e2e_asm_init_prod_end 0.000s 0.000us 0 1 0.00
rom_e2e_asm_init_rma 0.000s 0.000us 0 1 0.00
rom_e2e_keymgr_init 0 3 0.00
rom_e2e_keymgr_init_rom_ext_meas 0.000s 0.000us 0 1 0.00
rom_e2e_keymgr_init_rom_ext_no_meas 0.000s 0.000us 0 1 0.00
rom_e2e_keymgr_init_rom_ext_invalid_meas 0.000s 0.000us 0 1 0.00
rom_e2e_static_critical 0 1 0.00
rom_e2e_static_critical 0.000s 0.000us 0 1 0.00
Testpoint Test Max Runtime Sim Time Pass Total %
chip_sw_aes_masking_off 0 1 0.00
chip_sw_aes_masking_off 0.000s 0.000us 0 1 0.00
chip_sw_rv_core_ibex_lockstep_glitch 0 1 0.00
chip_sw_rv_core_ibex_lockstep_glitch 0.000s 0.000us 0 1 0.00
Testpoint Test Max Runtime Sim Time Pass Total %
chip_rv_dm_perform_debug 0 3 0.00
rom_e2e_jtag_debug_test_unlocked0 0.000s 0.000us 0 1 0.00
rom_e2e_jtag_debug_dev 0.000s 0.000us 0 1 0.00
rom_e2e_jtag_debug_rma 0.000s 0.000us 0 1 0.00
chip_sw_rv_dm_access_after_hw_reset 0 1 0.00
chip_sw_rv_dm_access_after_escalation_reset 0.000s 0.000us 0 1 0.00
chip_sw_plic_alerts 0 1 0.00
chip_sw_all_escalation_resets 0.000s 0.000us 0 1 0.00
chip_sw_otp_ctrl_vendor_test_csr_access 0 1 0.00
chip_sw_otp_ctrl_vendor_test_csr_access 0.000s 0.000us 0 1 0.00
chip_sw_otp_ctrl_escalation 0 1 0.00
chip_sw_otp_ctrl_escalation 0.000s 0.000us 0 1 0.00
chip_sw_coremark 0 1 0.00
chip_sw_coremark 0.000s 0.000us 0 1 0.00
chip_sw_power_max_load 0 1 0.00
chip_sw_power_virus 0.000s 0.000us 0 1 0.00
rom_e2e_debug 0 3 0.00
rom_e2e_jtag_debug_test_unlocked0 0.000s 0.000us 0 1 0.00
rom_e2e_jtag_debug_dev 0.000s 0.000us 0 1 0.00
rom_e2e_jtag_debug_rma 0.000s 0.000us 0 1 0.00
rom_e2e_jtag_inject 0 3 0.00
rom_e2e_jtag_inject_test_unlocked0 0.000s 0.000us 0 1 0.00
rom_e2e_jtag_inject_dev 0.000s 0.000us 0 1 0.00
rom_e2e_jtag_inject_rma 0.000s 0.000us 0 1 0.00
rom_e2e_self_hash 0 1 0.00
rom_e2e_self_hash 0.000s 0.000us 0 1 0.00
Testpoint Test Max Runtime Sim Time Pass Total %
Unmapped 0 19 0.00
chip_sw_rstmgr_rst_cnsty_escalation 0.000s 0.000us 0 1 0.00
chip_sw_entropy_src_kat_test 0.000s 0.000us 0 1 0.00
chip_sw_entropy_src_ast_rng_req 0.000s 0.000us 0 1 0.00
chip_plic_all_irqs_0 0.000s 0.000us 0 1 0.00
chip_plic_all_irqs_10 0.000s 0.000us 0 1 0.00
chip_sw_dma_inline_hashing 0.000s 0.000us 0 1 0.00
chip_sw_dma_abort 0.000s 0.000us 0 1 0.00
rom_e2e_sigverify_mod_exp_test_unlocked0_otbn 0.000s 0.000us 0 1 0.00
rom_e2e_sigverify_mod_exp_test_unlocked0_sw 0.000s 0.000us 0 1 0.00
rom_e2e_sigverify_mod_exp_dev_otbn 0.000s 0.000us 0 1 0.00
rom_e2e_sigverify_mod_exp_dev_sw 0.000s 0.000us 0 1 0.00
rom_e2e_sigverify_mod_exp_prod_otbn 0.000s 0.000us 0 1 0.00
rom_e2e_sigverify_mod_exp_prod_sw 0.000s 0.000us 0 1 0.00
rom_e2e_sigverify_mod_exp_prod_end_otbn 0.000s 0.000us 0 1 0.00
rom_e2e_sigverify_mod_exp_prod_end_sw 0.000s 0.000us 0 1 0.00
rom_e2e_sigverify_mod_exp_rma_otbn 0.000s 0.000us 0 1 0.00
rom_e2e_sigverify_mod_exp_rma_sw 0.000s 0.000us 0 1 0.00
chip_sw_entropy_src_smoketest 0.000s 0.000us 0 1 0.00
chip_sw_mbx_smoketest 0.000s 0.000us 0 1 0.00