Simulation Results: clkmgr

 
27/11/2025 16:08:38 sha: 8a15de8 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 72.86 %
  • code
  • 68.62 %
  • assert
  • 88.43 %
  • func
  • 61.52 %
  • line
  • 81.68 %
  • branch
  • 86.59 %
  • cond
  • 78.11 %
  • toggle
  • 96.70 %
  • FSM
  • 0.00 %
Validation stages
V1
25.00%
V2
57.89%
V2S
35.29%
V3
0.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
clkmgr_smoke 1.080s 21.847us 1 1 100.00
csr_hw_reset 1 1 100.00
clkmgr_csr_hw_reset 0.850s 20.484us 1 1 100.00
csr_rw 0 1 0.00
clkmgr_csr_rw 0.740s 7.254us 0 1 0.00
csr_bit_bash 0 1 0.00
clkmgr_csr_bit_bash 1.770s 139.805us 0 1 0.00
csr_aliasing 0 1 0.00
clkmgr_csr_aliasing 0.880s 31.752us 0 1 0.00
csr_mem_rw_with_rand_reset 0 1 0.00
clkmgr_csr_mem_rw_with_rand_reset 0.600s 2.499us 0 1 0.00
regwen_csr_and_corresponding_lockable_csr 0 2 0.00
clkmgr_csr_rw 0.740s 7.254us 0 1 0.00
clkmgr_csr_aliasing 0.880s 31.752us 0 1 0.00
Testpoint Test Max Runtime Sim Time Pass Total %
peri_enables 1 1 100.00
clkmgr_peri 1.370s 92.964us 1 1 100.00
trans_enables 1 1 100.00
clkmgr_trans 1.030s 43.569us 1 1 100.00
clk_status 1 1 100.00
clkmgr_clk_status 0.730s 16.238us 1 1 100.00
jitter 1 1 100.00
clkmgr_smoke 1.080s 21.847us 1 1 100.00
frequency 0 1 0.00
clkmgr_frequency 0.830s 19.927us 0 1 0.00
frequency_timeout 0 1 0.00
clkmgr_frequency_timeout 0.690s 3.481us 0 1 0.00
frequency_overflow 0 1 0.00
clkmgr_frequency 0.830s 19.927us 0 1 0.00
stress_all 0 1 0.00
clkmgr_stress_all 1.500s 79.353us 0 1 0.00
alert_test 1 1 100.00
clkmgr_alert_test 1.000s 50.062us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
clkmgr_tl_errors 0.980s 18.426us 1 1 100.00
tl_d_illegal_access 1 1 100.00
clkmgr_tl_errors 0.980s 18.426us 1 1 100.00
tl_d_outstanding_access 2 4 50.00
clkmgr_csr_hw_reset 0.850s 20.484us 1 1 100.00
clkmgr_csr_rw 0.740s 7.254us 0 1 0.00
clkmgr_csr_aliasing 0.880s 31.752us 0 1 0.00
clkmgr_same_csr_outstanding 0.930s 32.878us 1 1 100.00
tl_d_partial_access 2 4 50.00
clkmgr_csr_hw_reset 0.850s 20.484us 1 1 100.00
clkmgr_csr_rw 0.740s 7.254us 0 1 0.00
clkmgr_csr_aliasing 0.880s 31.752us 0 1 0.00
clkmgr_same_csr_outstanding 0.930s 32.878us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 0 2 0.00
clkmgr_sec_cm 1.480s 76.486us 0 1 0.00
clkmgr_tl_intg_err 0.730s 14.966us 0 1 0.00
shadow_reg_update_error 1 1 100.00
clkmgr_shadow_reg_errors 1.350s 82.818us 1 1 100.00
shadow_reg_read_clear_staged_value 1 1 100.00
clkmgr_shadow_reg_errors 1.350s 82.818us 1 1 100.00
shadow_reg_storage_error 1 1 100.00
clkmgr_shadow_reg_errors 1.350s 82.818us 1 1 100.00
shadowed_reset_glitch 1 1 100.00
clkmgr_shadow_reg_errors 1.350s 82.818us 1 1 100.00
shadow_reg_update_error_with_csr_rw 0 1 0.00
clkmgr_shadow_reg_errors_with_csr_rw 0.680s 5.321us 0 1 0.00
sec_cm_bus_integrity 0 1 0.00
clkmgr_tl_intg_err 0.730s 14.966us 0 1 0.00
sec_cm_meas_clk_bkgn_chk 0 1 0.00
clkmgr_frequency 0.830s 19.927us 0 1 0.00
sec_cm_timeout_clk_bkgn_chk 0 1 0.00
clkmgr_frequency_timeout 0.690s 3.481us 0 1 0.00
sec_cm_meas_config_shadow 1 1 100.00
clkmgr_shadow_reg_errors 1.350s 82.818us 1 1 100.00
sec_cm_idle_intersig_mubi 1 1 100.00
clkmgr_idle_intersig_mubi 1.100s 49.180us 1 1 100.00
sec_cm_jitter_config_mubi 0 1 0.00
clkmgr_csr_rw 0.740s 7.254us 0 1 0.00
sec_cm_idle_ctr_redun 0 1 0.00
clkmgr_sec_cm 1.480s 76.486us 0 1 0.00
sec_cm_meas_config_regwen 0 1 0.00
clkmgr_csr_rw 0.740s 7.254us 0 1 0.00
sec_cm_clk_ctrl_config_regwen 0 1 0.00
clkmgr_csr_rw 0.740s 7.254us 0 1 0.00
prim_count_check 0 1 0.00
clkmgr_sec_cm 1.480s 76.486us 0 1 0.00
Testpoint Test Max Runtime Sim Time Pass Total %
regwen 0 1 0.00
clkmgr_regwen 1.000s 34.098us 0 1 0.00
stress_all_with_rand_reset 0 1 0.00
clkmgr_stress_all_with_rand_reset 4.000s 324.051us 0 1 0.00