Simulation Results: csrng

 
27/11/2025 16:08:38 sha: 8a15de8 json Branch: master Tool: xcelium [unknown]
Coverage statistics
Validation stages
V1
100.00%
V2
94.44%
V2S
96.00%
V3
0.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
csrng_smoke 2.000s 55.431us 1 1 100.00
csr_hw_reset 1 1 100.00
csrng_csr_hw_reset 2.000s 19.394us 1 1 100.00
csr_rw 1 1 100.00
csrng_csr_rw 2.000s 35.369us 1 1 100.00
csr_bit_bash 1 1 100.00
csrng_csr_bit_bash 10.000s 273.791us 1 1 100.00
csr_aliasing 1 1 100.00
csrng_csr_aliasing 3.000s 114.345us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
csrng_csr_mem_rw_with_rand_reset 2.000s 66.138us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
csrng_csr_rw 2.000s 35.369us 1 1 100.00
csrng_csr_aliasing 3.000s 114.345us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
interrupts 1 1 100.00
csrng_intr 4.000s 56.210us 1 1 100.00
alerts 1 1 100.00
csrng_alert 12.000s 763.471us 1 1 100.00
err 1 1 100.00
csrng_err 2.000s 25.694us 1 1 100.00
cmds 1 1 100.00
csrng_cmds 61.000s 2531.203us 1 1 100.00
life cycle 1 1 100.00
csrng_cmds 61.000s 2531.203us 1 1 100.00
stress_all 0 1 0.00
csrng_stress_all 0.000s 0.000us 0 1 0.00
intr_test 1 1 100.00
csrng_intr_test 1.000s 41.084us 1 1 100.00
alert_test 1 1 100.00
csrng_alert_test 2.000s 28.947us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
csrng_tl_errors 3.000s 215.668us 1 1 100.00
tl_d_illegal_access 1 1 100.00
csrng_tl_errors 3.000s 215.668us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
csrng_csr_hw_reset 2.000s 19.394us 1 1 100.00
csrng_csr_rw 2.000s 35.369us 1 1 100.00
csrng_csr_aliasing 3.000s 114.345us 1 1 100.00
csrng_same_csr_outstanding 3.000s 172.121us 1 1 100.00
tl_d_partial_access 4 4 100.00
csrng_csr_hw_reset 2.000s 19.394us 1 1 100.00
csrng_csr_rw 2.000s 35.369us 1 1 100.00
csrng_csr_aliasing 3.000s 114.345us 1 1 100.00
csrng_same_csr_outstanding 3.000s 172.121us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
csrng_tl_intg_err 5.000s 311.132us 1 1 100.00
csrng_sec_cm 5.000s 324.190us 1 1 100.00
sec_cm_config_regwen 2 2 100.00
csrng_csr_rw 2.000s 35.369us 1 1 100.00
csrng_regwen 2.000s 14.931us 1 1 100.00
sec_cm_config_mubi 1 1 100.00
csrng_alert 12.000s 763.471us 1 1 100.00
sec_cm_intersig_mubi 0 1 0.00
csrng_stress_all 0.000s 0.000us 0 1 0.00
sec_cm_main_sm_fsm_sparse 3 3 100.00
csrng_intr 4.000s 56.210us 1 1 100.00
csrng_err 2.000s 25.694us 1 1 100.00
csrng_sec_cm 5.000s 324.190us 1 1 100.00
sec_cm_updrsp_fsm_sparse 3 3 100.00
csrng_intr 4.000s 56.210us 1 1 100.00
csrng_err 2.000s 25.694us 1 1 100.00
csrng_sec_cm 5.000s 324.190us 1 1 100.00
sec_cm_update_fsm_sparse 3 3 100.00
csrng_intr 4.000s 56.210us 1 1 100.00
csrng_err 2.000s 25.694us 1 1 100.00
csrng_sec_cm 5.000s 324.190us 1 1 100.00
sec_cm_blk_enc_fsm_sparse 3 3 100.00
csrng_intr 4.000s 56.210us 1 1 100.00
csrng_err 2.000s 25.694us 1 1 100.00
csrng_sec_cm 5.000s 324.190us 1 1 100.00
sec_cm_outblk_fsm_sparse 3 3 100.00
csrng_intr 4.000s 56.210us 1 1 100.00
csrng_err 2.000s 25.694us 1 1 100.00
csrng_sec_cm 5.000s 324.190us 1 1 100.00
sec_cm_gen_cmd_ctr_redun 3 3 100.00
csrng_intr 4.000s 56.210us 1 1 100.00
csrng_err 2.000s 25.694us 1 1 100.00
csrng_sec_cm 5.000s 324.190us 1 1 100.00
sec_cm_drbg_upd_ctr_redun 3 3 100.00
csrng_intr 4.000s 56.210us 1 1 100.00
csrng_err 2.000s 25.694us 1 1 100.00
csrng_sec_cm 5.000s 324.190us 1 1 100.00
sec_cm_drbg_gen_ctr_redun 3 3 100.00
csrng_intr 4.000s 56.210us 1 1 100.00
csrng_err 2.000s 25.694us 1 1 100.00
csrng_sec_cm 5.000s 324.190us 1 1 100.00
sec_cm_ctrl_mubi 1 1 100.00
csrng_alert 12.000s 763.471us 1 1 100.00
sec_cm_main_sm_ctr_local_esc 2 2 100.00
csrng_intr 4.000s 56.210us 1 1 100.00
csrng_err 2.000s 25.694us 1 1 100.00
sec_cm_constants_lc_gated 0 1 0.00
csrng_stress_all 0.000s 0.000us 0 1 0.00
sec_cm_sw_genbits_bus_consistency 1 1 100.00
csrng_alert 12.000s 763.471us 1 1 100.00
sec_cm_tile_link_bus_integrity 1 1 100.00
csrng_tl_intg_err 5.000s 311.132us 1 1 100.00
sec_cm_aes_cipher_fsm_sparse 3 3 100.00
csrng_intr 4.000s 56.210us 1 1 100.00
csrng_err 2.000s 25.694us 1 1 100.00
csrng_sec_cm 5.000s 324.190us 1 1 100.00
sec_cm_aes_cipher_fsm_redun 2 2 100.00
csrng_intr 4.000s 56.210us 1 1 100.00
csrng_err 2.000s 25.694us 1 1 100.00
sec_cm_aes_cipher_ctrl_sparse 2 2 100.00
csrng_intr 4.000s 56.210us 1 1 100.00
csrng_err 2.000s 25.694us 1 1 100.00
sec_cm_aes_cipher_fsm_local_esc 2 2 100.00
csrng_intr 4.000s 56.210us 1 1 100.00
csrng_err 2.000s 25.694us 1 1 100.00
sec_cm_aes_cipher_ctr_redun 3 3 100.00
csrng_intr 4.000s 56.210us 1 1 100.00
csrng_err 2.000s 25.694us 1 1 100.00
csrng_sec_cm 5.000s 324.190us 1 1 100.00
sec_cm_aes_cipher_data_reg_local_esc 2 2 100.00
csrng_intr 4.000s 56.210us 1 1 100.00
csrng_err 2.000s 25.694us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 0 1 0.00
csrng_stress_all_with_rand_reset 0.000s 0.000us 0 1 0.00