| V1 |
|
100.00% |
| V2 |
|
85.71% |
| V2S |
|
83.33% |
| unmapped |
|
66.67% |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| dma_memory_smoke | 1 | 1 | 100.00 | |||
| dma_memory_smoke | 4.000s | 528.984us | 1 | 1 | 100.00 | |
| dma_handshake_smoke | 1 | 1 | 100.00 | |||
| dma_handshake_smoke | 7.000s | 4418.359us | 1 | 1 | 100.00 | |
| dma_generic_smoke | 1 | 1 | 100.00 | |||
| dma_generic_smoke | 6.000s | 668.583us | 1 | 1 | 100.00 | |
| csr_hw_reset | 1 | 1 | 100.00 | |||
| dma_csr_hw_reset | 2.000s | 187.201us | 1 | 1 | 100.00 | |
| csr_rw | 1 | 1 | 100.00 | |||
| dma_csr_rw | 2.000s | 58.945us | 1 | 1 | 100.00 | |
| csr_bit_bash | 1 | 1 | 100.00 | |||
| dma_csr_bit_bash | 11.000s | 1354.026us | 1 | 1 | 100.00 | |
| csr_aliasing | 1 | 1 | 100.00 | |||
| dma_csr_aliasing | 7.000s | 1807.463us | 1 | 1 | 100.00 | |
| csr_mem_rw_with_rand_reset | 1 | 1 | 100.00 | |||
| dma_csr_mem_rw_with_rand_reset | 2.000s | 39.758us | 1 | 1 | 100.00 | |
| regwen_csr_and_corresponding_lockable_csr | 2 | 2 | 100.00 | |||
| dma_csr_rw | 2.000s | 58.945us | 1 | 1 | 100.00 | |
| dma_csr_aliasing | 7.000s | 1807.463us | 1 | 1 | 100.00 | |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| dma_memory_region_lock | 1 | 1 | 100.00 | |||
| dma_memory_region_lock | 55.000s | 3202.448us | 1 | 1 | 100.00 | |
| dma_memory_tl_error | 0 | 1 | 0.00 | |||
| dma_memory_stress | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| dma_handshake_tl_error | 1 | 1 | 100.00 | |||
| dma_handshake_stress | 145.000s | 31131.105us | 1 | 1 | 100.00 | |
| dma_handshake_stress | 1 | 1 | 100.00 | |||
| dma_handshake_stress | 145.000s | 31131.105us | 1 | 1 | 100.00 | |
| dma_memory_stress | 0 | 1 | 0.00 | |||
| dma_memory_stress | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| dma_generic_stress | 0 | 1 | 0.00 | |||
| dma_generic_stress | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| dma_handshake_mem_buffer_overflow | 1 | 1 | 100.00 | |||
| dma_handshake_stress | 145.000s | 31131.105us | 1 | 1 | 100.00 | |
| dma_abort | 1 | 1 | 100.00 | |||
| dma_abort | 7.000s | 397.032us | 1 | 1 | 100.00 | |
| dma_stress_all | 1 | 1 | 100.00 | |||
| dma_stress_all | 91.000s | 7844.079us | 1 | 1 | 100.00 | |
| alert_test | 1 | 1 | 100.00 | |||
| dma_alert_test | 1.000s | 52.781us | 1 | 1 | 100.00 | |
| intr_test | 1 | 1 | 100.00 | |||
| dma_intr_test | 1.000s | 22.578us | 1 | 1 | 100.00 | |
| tl_d_oob_addr_access | 1 | 1 | 100.00 | |||
| dma_tl_errors | 2.000s | 24.338us | 1 | 1 | 100.00 | |
| tl_d_illegal_access | 1 | 1 | 100.00 | |||
| dma_tl_errors | 2.000s | 24.338us | 1 | 1 | 100.00 | |
| tl_d_outstanding_access | 4 | 4 | 100.00 | |||
| dma_csr_hw_reset | 2.000s | 187.201us | 1 | 1 | 100.00 | |
| dma_csr_rw | 2.000s | 58.945us | 1 | 1 | 100.00 | |
| dma_csr_aliasing | 7.000s | 1807.463us | 1 | 1 | 100.00 | |
| dma_same_csr_outstanding | 2.000s | 1259.881us | 1 | 1 | 100.00 | |
| tl_d_partial_access | 4 | 4 | 100.00 | |||
| dma_csr_hw_reset | 2.000s | 187.201us | 1 | 1 | 100.00 | |
| dma_csr_rw | 2.000s | 58.945us | 1 | 1 | 100.00 | |
| dma_csr_aliasing | 7.000s | 1807.463us | 1 | 1 | 100.00 | |
| dma_same_csr_outstanding | 2.000s | 1259.881us | 1 | 1 | 100.00 | |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| dma_illegal_addr_range | 2 | 3 | 66.67 | |||
| dma_mem_enabled | 21.000s | 1443.749us | 1 | 1 | 100.00 | |
| dma_generic_stress | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| dma_handshake_stress | 145.000s | 31131.105us | 1 | 1 | 100.00 | |
| dma_config_lock | 1 | 1 | 100.00 | |||
| dma_config_lock | 6.000s | 381.895us | 1 | 1 | 100.00 | |
| tl_intg_err | 2 | 2 | 100.00 | |||
| dma_sec_cm | 2.000s | 12.483us | 1 | 1 | 100.00 | |
| dma_tl_intg_err | 3.000s | 98.351us | 1 | 1 | 100.00 | |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| Unmapped | 2 | 3 | 66.67 | |||
| dma_short_transfer | 60.000s | 33163.675us | 1 | 1 | 100.00 | |
| dma_longer_transfer | 9.000s | 443.536us | 1 | 1 | 100.00 | |
| dma_stress_all_with_rand_reset | 21.000s | 2074.375us | 0 | 1 | 0.00 | |