Simulation Results: edn

 
27/11/2025 16:08:38 sha: 8a15de8 json Branch: master Tool: vcs [unknown]
Coverage statistics
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
0.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
edn_smoke 1.160s 18.242us 1 1 100.00
csr_hw_reset 1 1 100.00
edn_csr_hw_reset 1.040s 18.154us 1 1 100.00
csr_rw 1 1 100.00
edn_csr_rw 1.070s 163.831us 1 1 100.00
csr_bit_bash 1 1 100.00
edn_csr_bit_bash 3.760s 360.149us 1 1 100.00
csr_aliasing 1 1 100.00
edn_csr_aliasing 1.500s 35.316us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
edn_csr_mem_rw_with_rand_reset 1.290s 141.745us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
edn_csr_rw 1.070s 163.831us 1 1 100.00
edn_csr_aliasing 1.500s 35.316us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
firmware 1 1 100.00
edn_genbits 1.670s 43.410us 1 1 100.00
csrng_commands 1 1 100.00
edn_genbits 1.670s 43.410us 1 1 100.00
genbits 1 1 100.00
edn_genbits 1.670s 43.410us 1 1 100.00
interrupts 1 1 100.00
edn_intr 1.090s 22.432us 1 1 100.00
alerts 1 1 100.00
edn_alert 0.970s 74.327us 1 1 100.00
errs 1 1 100.00
edn_err 0.920s 32.743us 1 1 100.00
disable 2 2 100.00
edn_disable 0.930s 34.627us 1 1 100.00
edn_disable_auto_req_mode 1.030s 17.192us 1 1 100.00
stress_all 1 1 100.00
edn_stress_all 3.000s 645.577us 1 1 100.00
intr_test 1 1 100.00
edn_intr_test 1.150s 17.716us 1 1 100.00
alert_test 1 1 100.00
edn_alert_test 1.020s 24.156us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
edn_tl_errors 1.600s 42.657us 1 1 100.00
tl_d_illegal_access 1 1 100.00
edn_tl_errors 1.600s 42.657us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
edn_csr_hw_reset 1.040s 18.154us 1 1 100.00
edn_csr_rw 1.070s 163.831us 1 1 100.00
edn_csr_aliasing 1.500s 35.316us 1 1 100.00
edn_same_csr_outstanding 1.310s 91.153us 1 1 100.00
tl_d_partial_access 4 4 100.00
edn_csr_hw_reset 1.040s 18.154us 1 1 100.00
edn_csr_rw 1.070s 163.831us 1 1 100.00
edn_csr_aliasing 1.500s 35.316us 1 1 100.00
edn_same_csr_outstanding 1.310s 91.153us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
edn_tl_intg_err 2.210s 453.628us 1 1 100.00
edn_sec_cm 4.310s 283.263us 1 1 100.00
sec_cm_config_regwen 1 1 100.00
edn_regwen 0.920s 123.603us 1 1 100.00
sec_cm_config_mubi 1 1 100.00
edn_alert 0.970s 74.327us 1 1 100.00
sec_cm_main_sm_fsm_sparse 1 1 100.00
edn_sec_cm 4.310s 283.263us 1 1 100.00
sec_cm_ack_sm_fsm_sparse 1 1 100.00
edn_sec_cm 4.310s 283.263us 1 1 100.00
sec_cm_fifo_ctr_redun 1 1 100.00
edn_sec_cm 4.310s 283.263us 1 1 100.00
sec_cm_ctr_redun 1 1 100.00
edn_sec_cm 4.310s 283.263us 1 1 100.00
sec_cm_main_sm_ctr_local_esc 2 2 100.00
edn_alert 0.970s 74.327us 1 1 100.00
edn_sec_cm 4.310s 283.263us 1 1 100.00
sec_cm_cs_rdata_bus_consistency 1 1 100.00
edn_alert 0.970s 74.327us 1 1 100.00
sec_cm_tile_link_bus_integrity 1 1 100.00
edn_tl_intg_err 2.210s 453.628us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 0 1 0.00
edn_stress_all_with_rand_reset 0.000s 0.000us 0 1 0.00