| V1 |
|
50.00% |
| V2 |
|
48.15% |
| V2S |
|
70.00% |
| V3 |
|
0.00% |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| smoke | 1 | 1 | 100.00 | |||
| entropy_src_smoke | 2.000s | 106.591us | 1 | 1 | 100.00 | |
| csr_hw_reset | 1 | 1 | 100.00 | |||
| entropy_src_csr_hw_reset | 2.000s | 70.163us | 1 | 1 | 100.00 | |
| csr_rw | 1 | 1 | 100.00 | |||
| entropy_src_csr_rw | 2.000s | 46.913us | 1 | 1 | 100.00 | |
| csr_bit_bash | 0 | 1 | 0.00 | |||
| entropy_src_csr_bit_bash | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| csr_aliasing | 0 | 1 | 0.00 | |||
| entropy_src_csr_aliasing | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| csr_mem_rw_with_rand_reset | 0 | 1 | 0.00 | |||
| entropy_src_csr_mem_rw_with_rand_reset | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| regwen_csr_and_corresponding_lockable_csr | 1 | 2 | 50.00 | |||
| entropy_src_csr_rw | 2.000s | 46.913us | 1 | 1 | 100.00 | |
| entropy_src_csr_aliasing | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| firmware | 1 | 3 | 33.33 | |||
| entropy_src_smoke | 2.000s | 106.591us | 1 | 1 | 100.00 | |
| entropy_src_rng | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| entropy_src_fw_ov | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| firmware_mode | 0 | 1 | 0.00 | |||
| entropy_src_fw_ov | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| rng_mode | 0 | 1 | 0.00 | |||
| entropy_src_rng | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| rng_max_rate | 0 | 1 | 0.00 | |||
| entropy_src_rng_max_rate | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| health_checks | 0 | 1 | 0.00 | |||
| entropy_src_rng | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| conditioning | 0 | 1 | 0.00 | |||
| entropy_src_rng | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| interrupts | 1 | 2 | 50.00 | |||
| entropy_src_rng | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| entropy_src_intr | 2.000s | 26.396us | 1 | 1 | 100.00 | |
| alerts | 1 | 2 | 50.00 | |||
| entropy_src_rng | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| entropy_src_functional_alerts | 6.000s | 325.324us | 1 | 1 | 100.00 | |
| stress_all | 0 | 1 | 0.00 | |||
| entropy_src_stress_all | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| functional_errors | 1 | 1 | 100.00 | |||
| entropy_src_functional_errors | 2.000s | 61.889us | 1 | 1 | 100.00 | |
| firmware_ov_read_contiguous_data | 1 | 1 | 100.00 | |||
| entropy_src_fw_ov_contiguous | 12.000s | 231.011us | 1 | 1 | 100.00 | |
| intr_test | 1 | 1 | 100.00 | |||
| entropy_src_intr_test | 2.000s | 82.398us | 1 | 1 | 100.00 | |
| alert_test | 1 | 1 | 100.00 | |||
| entropy_src_alert_test | 2.000s | 31.053us | 1 | 1 | 100.00 | |
| tl_d_oob_addr_access | 1 | 1 | 100.00 | |||
| entropy_src_tl_errors | 2.000s | 67.479us | 1 | 1 | 100.00 | |
| tl_d_illegal_access | 1 | 1 | 100.00 | |||
| entropy_src_tl_errors | 2.000s | 67.479us | 1 | 1 | 100.00 | |
| tl_d_outstanding_access | 2 | 4 | 50.00 | |||
| entropy_src_csr_hw_reset | 2.000s | 70.163us | 1 | 1 | 100.00 | |
| entropy_src_csr_rw | 2.000s | 46.913us | 1 | 1 | 100.00 | |
| entropy_src_csr_aliasing | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| entropy_src_same_csr_outstanding | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| tl_d_partial_access | 2 | 4 | 50.00 | |||
| entropy_src_csr_hw_reset | 2.000s | 70.163us | 1 | 1 | 100.00 | |
| entropy_src_csr_rw | 2.000s | 46.913us | 1 | 1 | 100.00 | |
| entropy_src_csr_aliasing | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| entropy_src_same_csr_outstanding | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| tl_intg_err | 2 | 2 | 100.00 | |||
| entropy_src_sec_cm | 3.000s | 1765.369us | 1 | 1 | 100.00 | |
| entropy_src_tl_intg_err | 2.000s | 124.988us | 1 | 1 | 100.00 | |
| sec_cm_config_regwen | 1 | 2 | 50.00 | |||
| entropy_src_rng | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| entropy_src_cfg_regwen | 3.000s | 39.094us | 1 | 1 | 100.00 | |
| sec_cm_config_mubi | 0 | 1 | 0.00 | |||
| entropy_src_rng | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| sec_cm_config_redun | 0 | 1 | 0.00 | |||
| entropy_src_rng | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| sec_cm_intersig_mubi | 0 | 2 | 0.00 | |||
| entropy_src_rng | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| entropy_src_fw_ov | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| sec_cm_main_sm_fsm_sparse | 2 | 2 | 100.00 | |||
| entropy_src_functional_errors | 2.000s | 61.889us | 1 | 1 | 100.00 | |
| entropy_src_sec_cm | 3.000s | 1765.369us | 1 | 1 | 100.00 | |
| sec_cm_ack_sm_fsm_sparse | 2 | 2 | 100.00 | |||
| entropy_src_functional_errors | 2.000s | 61.889us | 1 | 1 | 100.00 | |
| entropy_src_sec_cm | 3.000s | 1765.369us | 1 | 1 | 100.00 | |
| sec_cm_rng_bkgn_chk | 0 | 1 | 0.00 | |||
| entropy_src_rng | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| sec_cm_fifo_ctr_redun | 2 | 2 | 100.00 | |||
| entropy_src_functional_errors | 2.000s | 61.889us | 1 | 1 | 100.00 | |
| entropy_src_sec_cm | 3.000s | 1765.369us | 1 | 1 | 100.00 | |
| sec_cm_ctr_redun | 2 | 2 | 100.00 | |||
| entropy_src_functional_errors | 2.000s | 61.889us | 1 | 1 | 100.00 | |
| entropy_src_sec_cm | 3.000s | 1765.369us | 1 | 1 | 100.00 | |
| sec_cm_ctr_local_esc | 1 | 1 | 100.00 | |||
| entropy_src_functional_errors | 2.000s | 61.889us | 1 | 1 | 100.00 | |
| sec_cm_esfinal_rdata_bus_consistency | 1 | 1 | 100.00 | |||
| entropy_src_functional_alerts | 6.000s | 325.324us | 1 | 1 | 100.00 | |
| sec_cm_tile_link_bus_integrity | 1 | 1 | 100.00 | |||
| entropy_src_tl_intg_err | 2.000s | 124.988us | 1 | 1 | 100.00 | |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| external_health_tests | 0 | 1 | 0.00 | |||
| entropy_src_rng_with_xht_rsps | 0.000s | 0.000us | 0 | 1 | 0.00 | |