Simulation Results: hmac

 
27/11/2025 16:08:38 sha: 8a15de8 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 79.42 %
  • code
  • 97.13 %
  • assert
  • 96.42 %
  • func
  • 44.71 %
  • line
  • 99.74 %
  • branch
  • 99.01 %
  • cond
  • 95.73 %
  • toggle
  • 100.00 %
  • FSM
  • 91.18 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
100.00%
unmapped
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
hmac_smoke 11.020s 2550.230us 1 1 100.00
csr_hw_reset 1 1 100.00
hmac_csr_hw_reset 0.680s 55.853us 1 1 100.00
csr_rw 1 1 100.00
hmac_csr_rw 0.920s 56.506us 1 1 100.00
csr_bit_bash 1 1 100.00
hmac_csr_bit_bash 7.920s 1095.346us 1 1 100.00
csr_aliasing 1 1 100.00
hmac_csr_aliasing 2.370s 158.299us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
hmac_csr_mem_rw_with_rand_reset 416.010s 63067.356us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
hmac_csr_rw 0.920s 56.506us 1 1 100.00
hmac_csr_aliasing 2.370s 158.299us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
long_msg 1 1 100.00
hmac_long_msg 29.100s 2946.828us 1 1 100.00
back_pressure 1 1 100.00
hmac_back_pressure 9.280s 2955.580us 1 1 100.00
test_vectors 6 6 100.00
hmac_test_sha256_vectors 7.900s 241.264us 1 1 100.00
hmac_test_sha384_vectors 388.940s 12250.713us 1 1 100.00
hmac_test_sha512_vectors 362.680s 23770.292us 1 1 100.00
hmac_test_hmac256_vectors 8.120s 1509.792us 1 1 100.00
hmac_test_hmac384_vectors 7.360s 464.934us 1 1 100.00
hmac_test_hmac512_vectors 14.310s 2284.019us 1 1 100.00
burst_wr 1 1 100.00
hmac_burst_wr 14.720s 3210.657us 1 1 100.00
datapath_stress 1 1 100.00
hmac_datapath_stress 348.720s 2859.603us 1 1 100.00
error 1 1 100.00
hmac_error 38.790s 5321.845us 1 1 100.00
wipe_secret 1 1 100.00
hmac_wipe_secret 33.450s 17094.903us 1 1 100.00
save_and_restore 6 6 100.00
hmac_smoke 11.020s 2550.230us 1 1 100.00
hmac_long_msg 29.100s 2946.828us 1 1 100.00
hmac_back_pressure 9.280s 2955.580us 1 1 100.00
hmac_datapath_stress 348.720s 2859.603us 1 1 100.00
hmac_burst_wr 14.720s 3210.657us 1 1 100.00
hmac_stress_all 113.600s 3185.202us 1 1 100.00
fifo_empty_status_interrupt 11 11 100.00
hmac_smoke 11.020s 2550.230us 1 1 100.00
hmac_long_msg 29.100s 2946.828us 1 1 100.00
hmac_back_pressure 9.280s 2955.580us 1 1 100.00
hmac_datapath_stress 348.720s 2859.603us 1 1 100.00
hmac_wipe_secret 33.450s 17094.903us 1 1 100.00
hmac_test_sha256_vectors 7.900s 241.264us 1 1 100.00
hmac_test_sha384_vectors 388.940s 12250.713us 1 1 100.00
hmac_test_sha512_vectors 362.680s 23770.292us 1 1 100.00
hmac_test_hmac256_vectors 8.120s 1509.792us 1 1 100.00
hmac_test_hmac384_vectors 7.360s 464.934us 1 1 100.00
hmac_test_hmac512_vectors 14.310s 2284.019us 1 1 100.00
wide_digest_configurable_key_length 14 14 100.00
hmac_smoke 11.020s 2550.230us 1 1 100.00
hmac_long_msg 29.100s 2946.828us 1 1 100.00
hmac_back_pressure 9.280s 2955.580us 1 1 100.00
hmac_datapath_stress 348.720s 2859.603us 1 1 100.00
hmac_burst_wr 14.720s 3210.657us 1 1 100.00
hmac_error 38.790s 5321.845us 1 1 100.00
hmac_wipe_secret 33.450s 17094.903us 1 1 100.00
hmac_test_sha256_vectors 7.900s 241.264us 1 1 100.00
hmac_test_sha384_vectors 388.940s 12250.713us 1 1 100.00
hmac_test_sha512_vectors 362.680s 23770.292us 1 1 100.00
hmac_test_hmac256_vectors 8.120s 1509.792us 1 1 100.00
hmac_test_hmac384_vectors 7.360s 464.934us 1 1 100.00
hmac_test_hmac512_vectors 14.310s 2284.019us 1 1 100.00
hmac_stress_all 113.600s 3185.202us 1 1 100.00
stress_all 1 1 100.00
hmac_stress_all 113.600s 3185.202us 1 1 100.00
alert_test 1 1 100.00
hmac_alert_test 0.630s 37.432us 1 1 100.00
intr_test 1 1 100.00
hmac_intr_test 0.680s 38.096us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
hmac_tl_errors 2.310s 57.660us 1 1 100.00
tl_d_illegal_access 1 1 100.00
hmac_tl_errors 2.310s 57.660us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
hmac_csr_hw_reset 0.680s 55.853us 1 1 100.00
hmac_csr_rw 0.920s 56.506us 1 1 100.00
hmac_csr_aliasing 2.370s 158.299us 1 1 100.00
hmac_same_csr_outstanding 1.950s 49.192us 1 1 100.00
tl_d_partial_access 4 4 100.00
hmac_csr_hw_reset 0.680s 55.853us 1 1 100.00
hmac_csr_rw 0.920s 56.506us 1 1 100.00
hmac_csr_aliasing 2.370s 158.299us 1 1 100.00
hmac_same_csr_outstanding 1.950s 49.192us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
hmac_sec_cm 0.810s 119.333us 1 1 100.00
hmac_tl_intg_err 1.550s 268.211us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
hmac_tl_intg_err 1.550s 268.211us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
write_config_and_secret_key_during_msg_wr 1 1 100.00
hmac_smoke 11.020s 2550.230us 1 1 100.00
stress_reset 1 1 100.00
hmac_stress_reset 1.410s 68.499us 1 1 100.00
stress_all_with_rand_reset 1 1 100.00
hmac_stress_all_with_rand_reset 48.980s 9111.358us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
Unmapped 1 1 100.00
hmac_directed 0.980s 29.969us 1 1 100.00