| V1 |
|
100.00% |
| V2 |
|
90.00% |
| V2S |
|
71.43% |
| V3 |
|
0.00% |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| smoke | 1 | 1 | 100.00 | |||
| lc_ctrl_smoke | 1.810s | 39.674us | 1 | 1 | 100.00 | |
| csr_hw_reset | 1 | 1 | 100.00 | |||
| lc_ctrl_csr_hw_reset | 0.950s | 56.488us | 1 | 1 | 100.00 | |
| csr_rw | 1 | 1 | 100.00 | |||
| lc_ctrl_csr_rw | 0.880s | 21.448us | 1 | 1 | 100.00 | |
| csr_bit_bash | 1 | 1 | 100.00 | |||
| lc_ctrl_csr_bit_bash | 2.310s | 608.108us | 1 | 1 | 100.00 | |
| csr_aliasing | 1 | 1 | 100.00 | |||
| lc_ctrl_csr_aliasing | 0.900s | 96.518us | 1 | 1 | 100.00 | |
| csr_mem_rw_with_rand_reset | 1 | 1 | 100.00 | |||
| lc_ctrl_csr_mem_rw_with_rand_reset | 1.270s | 79.161us | 1 | 1 | 100.00 | |
| regwen_csr_and_corresponding_lockable_csr | 2 | 2 | 100.00 | |||
| lc_ctrl_csr_rw | 0.880s | 21.448us | 1 | 1 | 100.00 | |
| lc_ctrl_csr_aliasing | 0.900s | 96.518us | 1 | 1 | 100.00 | |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| state_post_trans | 1 | 1 | 100.00 | |||
| lc_ctrl_state_post_trans | 2.690s | 128.636us | 1 | 1 | 100.00 | |
| regwen_during_op | 1 | 1 | 100.00 | |||
| lc_ctrl_regwen_during_op | 6.740s | 212.258us | 1 | 1 | 100.00 | |
| rand_wr_claim_transition_if | 1 | 1 | 100.00 | |||
| lc_ctrl_claim_transition_if | 1.090s | 36.692us | 1 | 1 | 100.00 | |
| lc_prog_failure | 1 | 1 | 100.00 | |||
| lc_ctrl_prog_failure | 3.460s | 335.661us | 1 | 1 | 100.00 | |
| lc_state_failure | 0 | 1 | 0.00 | |||
| lc_ctrl_state_failure | 5.980s | 274.664us | 0 | 1 | 0.00 | |
| lc_errors | 1 | 1 | 100.00 | |||
| lc_ctrl_errors | 5.050s | 279.849us | 1 | 1 | 100.00 | |
| security_escalation | 5 | 7 | 71.43 | |||
| lc_ctrl_state_failure | 5.980s | 274.664us | 0 | 1 | 0.00 | |
| lc_ctrl_prog_failure | 3.460s | 335.661us | 1 | 1 | 100.00 | |
| lc_ctrl_errors | 5.050s | 279.849us | 1 | 1 | 100.00 | |
| lc_ctrl_security_escalation | 4.950s | 830.601us | 1 | 1 | 100.00 | |
| lc_ctrl_jtag_state_failure | 5.240s | 1087.001us | 0 | 1 | 0.00 | |
| lc_ctrl_jtag_prog_failure | 6.260s | 340.481us | 1 | 1 | 100.00 | |
| lc_ctrl_jtag_errors | 15.740s | 5823.917us | 1 | 1 | 100.00 | |
| jtag_access | 13 | 13 | 100.00 | |||
| lc_ctrl_jtag_csr_hw_reset | 1.800s | 136.300us | 1 | 1 | 100.00 | |
| lc_ctrl_jtag_csr_rw | 1.270s | 88.336us | 1 | 1 | 100.00 | |
| lc_ctrl_jtag_csr_bit_bash | 13.660s | 2885.647us | 1 | 1 | 100.00 | |
| lc_ctrl_jtag_csr_aliasing | 9.520s | 559.793us | 1 | 1 | 100.00 | |
| lc_ctrl_jtag_same_csr_outstanding | 1.230s | 17.970us | 1 | 1 | 100.00 | |
| lc_ctrl_jtag_csr_mem_rw_with_rand_reset | 2.390s | 463.429us | 1 | 1 | 100.00 | |
| lc_ctrl_jtag_alert_test | 1.280s | 624.879us | 1 | 1 | 100.00 | |
| lc_ctrl_jtag_smoke | 6.040s | 719.895us | 1 | 1 | 100.00 | |
| lc_ctrl_jtag_state_post_trans | 16.100s | 4081.684us | 1 | 1 | 100.00 | |
| lc_ctrl_jtag_prog_failure | 6.260s | 340.481us | 1 | 1 | 100.00 | |
| lc_ctrl_jtag_errors | 15.740s | 5823.917us | 1 | 1 | 100.00 | |
| lc_ctrl_jtag_access | 5.130s | 3134.543us | 1 | 1 | 100.00 | |
| lc_ctrl_jtag_regwen_during_op | 19.170s | 1004.778us | 1 | 1 | 100.00 | |
| jtag_priority | 1 | 1 | 100.00 | |||
| lc_ctrl_jtag_priority | 1.230s | 149.950us | 1 | 1 | 100.00 | |
| lc_ctrl_volatile_unlock | 1 | 1 | 100.00 | |||
| lc_ctrl_volatile_unlock_smoke | 1.120s | 36.413us | 1 | 1 | 100.00 | |
| stress_all | 0 | 1 | 0.00 | |||
| lc_ctrl_stress_all | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| alert_test | 1 | 1 | 100.00 | |||
| lc_ctrl_alert_test | 1.180s | 83.935us | 1 | 1 | 100.00 | |
| tl_d_oob_addr_access | 1 | 1 | 100.00 | |||
| lc_ctrl_tl_errors | 1.700s | 650.559us | 1 | 1 | 100.00 | |
| tl_d_illegal_access | 1 | 1 | 100.00 | |||
| lc_ctrl_tl_errors | 1.700s | 650.559us | 1 | 1 | 100.00 | |
| tl_d_outstanding_access | 4 | 4 | 100.00 | |||
| lc_ctrl_csr_hw_reset | 0.950s | 56.488us | 1 | 1 | 100.00 | |
| lc_ctrl_csr_rw | 0.880s | 21.448us | 1 | 1 | 100.00 | |
| lc_ctrl_csr_aliasing | 0.900s | 96.518us | 1 | 1 | 100.00 | |
| lc_ctrl_same_csr_outstanding | 1.230s | 34.625us | 1 | 1 | 100.00 | |
| tl_d_partial_access | 4 | 4 | 100.00 | |||
| lc_ctrl_csr_hw_reset | 0.950s | 56.488us | 1 | 1 | 100.00 | |
| lc_ctrl_csr_rw | 0.880s | 21.448us | 1 | 1 | 100.00 | |
| lc_ctrl_csr_aliasing | 0.900s | 96.518us | 1 | 1 | 100.00 | |
| lc_ctrl_same_csr_outstanding | 1.230s | 34.625us | 1 | 1 | 100.00 | |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| tl_intg_err | 2 | 2 | 100.00 | |||
| lc_ctrl_tl_intg_err | 2.000s | 492.741us | 1 | 1 | 100.00 | |
| lc_ctrl_sec_cm | 6.590s | 963.754us | 1 | 1 | 100.00 | |
| sec_cm_bus_integrity | 1 | 1 | 100.00 | |||
| lc_ctrl_tl_intg_err | 2.000s | 492.741us | 1 | 1 | 100.00 | |
| sec_cm_transition_config_regwen | 1 | 1 | 100.00 | |||
| lc_ctrl_regwen_during_op | 6.740s | 212.258us | 1 | 1 | 100.00 | |
| sec_cm_manuf_state_sparse | 1 | 2 | 50.00 | |||
| lc_ctrl_state_failure | 5.980s | 274.664us | 0 | 1 | 0.00 | |
| lc_ctrl_sec_cm | 6.590s | 963.754us | 1 | 1 | 100.00 | |
| sec_cm_transition_ctr_sparse | 1 | 2 | 50.00 | |||
| lc_ctrl_state_failure | 5.980s | 274.664us | 0 | 1 | 0.00 | |
| lc_ctrl_sec_cm | 6.590s | 963.754us | 1 | 1 | 100.00 | |
| sec_cm_manuf_state_bkgn_chk | 1 | 2 | 50.00 | |||
| lc_ctrl_state_failure | 5.980s | 274.664us | 0 | 1 | 0.00 | |
| lc_ctrl_sec_cm | 6.590s | 963.754us | 1 | 1 | 100.00 | |
| sec_cm_transition_ctr_bkgn_chk | 1 | 2 | 50.00 | |||
| lc_ctrl_state_failure | 5.980s | 274.664us | 0 | 1 | 0.00 | |
| lc_ctrl_sec_cm | 6.590s | 963.754us | 1 | 1 | 100.00 | |
| sec_cm_state_config_sparse | 1 | 2 | 50.00 | |||
| lc_ctrl_state_failure | 5.980s | 274.664us | 0 | 1 | 0.00 | |
| lc_ctrl_sec_cm | 6.590s | 963.754us | 1 | 1 | 100.00 | |
| sec_cm_main_fsm_sparse | 1 | 2 | 50.00 | |||
| lc_ctrl_state_failure | 5.980s | 274.664us | 0 | 1 | 0.00 | |
| lc_ctrl_sec_cm | 6.590s | 963.754us | 1 | 1 | 100.00 | |
| sec_cm_kmac_fsm_sparse | 1 | 2 | 50.00 | |||
| lc_ctrl_state_failure | 5.980s | 274.664us | 0 | 1 | 0.00 | |
| lc_ctrl_sec_cm | 6.590s | 963.754us | 1 | 1 | 100.00 | |
| sec_cm_main_fsm_local_esc | 1 | 2 | 50.00 | |||
| lc_ctrl_state_failure | 5.980s | 274.664us | 0 | 1 | 0.00 | |
| lc_ctrl_sec_cm | 6.590s | 963.754us | 1 | 1 | 100.00 | |
| sec_cm_main_fsm_global_esc | 1 | 1 | 100.00 | |||
| lc_ctrl_security_escalation | 4.950s | 830.601us | 1 | 1 | 100.00 | |
| sec_cm_main_ctrl_flow_consistency | 2 | 2 | 100.00 | |||
| lc_ctrl_state_post_trans | 2.690s | 128.636us | 1 | 1 | 100.00 | |
| lc_ctrl_jtag_state_post_trans | 16.100s | 4081.684us | 1 | 1 | 100.00 | |
| sec_cm_intersig_mubi | 1 | 1 | 100.00 | |||
| lc_ctrl_sec_mubi | 5.410s | 5751.310us | 1 | 1 | 100.00 | |
| sec_cm_token_valid_ctrl_mubi | 1 | 1 | 100.00 | |||
| lc_ctrl_sec_mubi | 5.410s | 5751.310us | 1 | 1 | 100.00 | |
| sec_cm_token_digest | 1 | 1 | 100.00 | |||
| lc_ctrl_sec_token_digest | 6.260s | 1740.656us | 1 | 1 | 100.00 | |
| sec_cm_token_mux_ctrl_redun | 1 | 1 | 100.00 | |||
| lc_ctrl_sec_token_mux | 6.260s | 432.723us | 1 | 1 | 100.00 | |
| sec_cm_token_valid_mux_redun | 1 | 1 | 100.00 | |||
| lc_ctrl_sec_token_mux | 6.260s | 432.723us | 1 | 1 | 100.00 | |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| stress_all_with_rand_reset | 0 | 1 | 0.00 | |||
| lc_ctrl_stress_all_with_rand_reset | 13.260s | 342.621us | 0 | 1 | 0.00 | |