Simulation Results: lc_ctrl

 
27/11/2025 16:08:38 sha: 8a15de8 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 91.43 %
  • code
  • 88.00 %
  • assert
  • 95.99 %
  • func
  • 90.29 %
  • line
  • 97.61 %
  • branch
  • 95.80 %
  • cond
  • 79.31 %
  • toggle
  • 83.56 %
  • FSM
  • 83.72 %
Validation stages
V1
100.00%
V2
90.00%
V2S
71.43%
V3
0.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
lc_ctrl_smoke 2.540s 353.975us 1 1 100.00
csr_hw_reset 1 1 100.00
lc_ctrl_csr_hw_reset 1.020s 17.947us 1 1 100.00
csr_rw 1 1 100.00
lc_ctrl_csr_rw 0.770s 22.974us 1 1 100.00
csr_bit_bash 1 1 100.00
lc_ctrl_csr_bit_bash 1.350s 297.195us 1 1 100.00
csr_aliasing 1 1 100.00
lc_ctrl_csr_aliasing 1.130s 30.291us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
lc_ctrl_csr_mem_rw_with_rand_reset 1.330s 31.575us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
lc_ctrl_csr_rw 0.770s 22.974us 1 1 100.00
lc_ctrl_csr_aliasing 1.130s 30.291us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
state_post_trans 1 1 100.00
lc_ctrl_state_post_trans 6.440s 403.167us 1 1 100.00
regwen_during_op 1 1 100.00
lc_ctrl_regwen_during_op 3.610s 214.207us 1 1 100.00
rand_wr_claim_transition_if 1 1 100.00
lc_ctrl_claim_transition_if 0.800s 32.405us 1 1 100.00
lc_prog_failure 1 1 100.00
lc_ctrl_prog_failure 3.040s 201.206us 1 1 100.00
lc_state_failure 0 1 0.00
lc_ctrl_state_failure 1.340s 2.613us 0 1 0.00
lc_errors 1 1 100.00
lc_ctrl_errors 5.070s 1624.856us 1 1 100.00
security_escalation 5 7 71.43
lc_ctrl_state_failure 1.340s 2.613us 0 1 0.00
lc_ctrl_prog_failure 3.040s 201.206us 1 1 100.00
lc_ctrl_errors 5.070s 1624.856us 1 1 100.00
lc_ctrl_security_escalation 5.220s 386.076us 1 1 100.00
lc_ctrl_jtag_state_failure 8.400s 3627.630us 0 1 0.00
lc_ctrl_jtag_prog_failure 3.090s 975.202us 1 1 100.00
lc_ctrl_jtag_errors 32.750s 3424.378us 1 1 100.00
jtag_access 13 13 100.00
lc_ctrl_jtag_csr_hw_reset 1.740s 175.632us 1 1 100.00
lc_ctrl_jtag_csr_rw 1.510s 89.145us 1 1 100.00
lc_ctrl_jtag_csr_bit_bash 6.710s 13515.137us 1 1 100.00
lc_ctrl_jtag_csr_aliasing 3.760s 401.830us 1 1 100.00
lc_ctrl_jtag_same_csr_outstanding 1.780s 47.961us 1 1 100.00
lc_ctrl_jtag_csr_mem_rw_with_rand_reset 3.320s 1628.027us 1 1 100.00
lc_ctrl_jtag_alert_test 0.890s 97.808us 1 1 100.00
lc_ctrl_jtag_smoke 5.100s 441.996us 1 1 100.00
lc_ctrl_jtag_state_post_trans 10.190s 1538.335us 1 1 100.00
lc_ctrl_jtag_prog_failure 3.090s 975.202us 1 1 100.00
lc_ctrl_jtag_errors 32.750s 3424.378us 1 1 100.00
lc_ctrl_jtag_access 7.010s 635.875us 1 1 100.00
lc_ctrl_jtag_regwen_during_op 12.350s 18641.813us 1 1 100.00
jtag_priority 1 1 100.00
lc_ctrl_jtag_priority 17.960s 2669.557us 1 1 100.00
lc_ctrl_volatile_unlock 1 1 100.00
lc_ctrl_volatile_unlock_smoke 0.840s 17.586us 1 1 100.00
stress_all 0 1 0.00
lc_ctrl_stress_all 8.070s 548.376us 0 1 0.00
alert_test 1 1 100.00
lc_ctrl_alert_test 1.370s 74.910us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
lc_ctrl_tl_errors 1.730s 76.981us 1 1 100.00
tl_d_illegal_access 1 1 100.00
lc_ctrl_tl_errors 1.730s 76.981us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
lc_ctrl_csr_hw_reset 1.020s 17.947us 1 1 100.00
lc_ctrl_csr_rw 0.770s 22.974us 1 1 100.00
lc_ctrl_csr_aliasing 1.130s 30.291us 1 1 100.00
lc_ctrl_same_csr_outstanding 1.190s 74.325us 1 1 100.00
tl_d_partial_access 4 4 100.00
lc_ctrl_csr_hw_reset 1.020s 17.947us 1 1 100.00
lc_ctrl_csr_rw 0.770s 22.974us 1 1 100.00
lc_ctrl_csr_aliasing 1.130s 30.291us 1 1 100.00
lc_ctrl_same_csr_outstanding 1.190s 74.325us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
lc_ctrl_tl_intg_err 1.940s 440.895us 1 1 100.00
lc_ctrl_sec_cm 8.870s 216.461us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
lc_ctrl_tl_intg_err 1.940s 440.895us 1 1 100.00
sec_cm_transition_config_regwen 1 1 100.00
lc_ctrl_regwen_during_op 3.610s 214.207us 1 1 100.00
sec_cm_manuf_state_sparse 1 2 50.00
lc_ctrl_state_failure 1.340s 2.613us 0 1 0.00
lc_ctrl_sec_cm 8.870s 216.461us 1 1 100.00
sec_cm_transition_ctr_sparse 1 2 50.00
lc_ctrl_state_failure 1.340s 2.613us 0 1 0.00
lc_ctrl_sec_cm 8.870s 216.461us 1 1 100.00
sec_cm_manuf_state_bkgn_chk 1 2 50.00
lc_ctrl_state_failure 1.340s 2.613us 0 1 0.00
lc_ctrl_sec_cm 8.870s 216.461us 1 1 100.00
sec_cm_transition_ctr_bkgn_chk 1 2 50.00
lc_ctrl_state_failure 1.340s 2.613us 0 1 0.00
lc_ctrl_sec_cm 8.870s 216.461us 1 1 100.00
sec_cm_state_config_sparse 1 2 50.00
lc_ctrl_state_failure 1.340s 2.613us 0 1 0.00
lc_ctrl_sec_cm 8.870s 216.461us 1 1 100.00
sec_cm_main_fsm_sparse 1 2 50.00
lc_ctrl_state_failure 1.340s 2.613us 0 1 0.00
lc_ctrl_sec_cm 8.870s 216.461us 1 1 100.00
sec_cm_kmac_fsm_sparse 1 2 50.00
lc_ctrl_state_failure 1.340s 2.613us 0 1 0.00
lc_ctrl_sec_cm 8.870s 216.461us 1 1 100.00
sec_cm_main_fsm_local_esc 1 2 50.00
lc_ctrl_state_failure 1.340s 2.613us 0 1 0.00
lc_ctrl_sec_cm 8.870s 216.461us 1 1 100.00
sec_cm_main_fsm_global_esc 1 1 100.00
lc_ctrl_security_escalation 5.220s 386.076us 1 1 100.00
sec_cm_main_ctrl_flow_consistency 2 2 100.00
lc_ctrl_state_post_trans 6.440s 403.167us 1 1 100.00
lc_ctrl_jtag_state_post_trans 10.190s 1538.335us 1 1 100.00
sec_cm_intersig_mubi 1 1 100.00
lc_ctrl_sec_mubi 9.140s 2136.537us 1 1 100.00
sec_cm_token_valid_ctrl_mubi 1 1 100.00
lc_ctrl_sec_mubi 9.140s 2136.537us 1 1 100.00
sec_cm_token_digest 1 1 100.00
lc_ctrl_sec_token_digest 7.660s 273.620us 1 1 100.00
sec_cm_token_mux_ctrl_redun 1 1 100.00
lc_ctrl_sec_token_mux 4.580s 374.470us 1 1 100.00
sec_cm_token_valid_mux_redun 1 1 100.00
lc_ctrl_sec_token_mux 4.580s 374.470us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 0 1 0.00
lc_ctrl_stress_all_with_rand_reset 32.000s 3222.846us 0 1 0.00