| V1 |
|
100.00% |
| V2 |
|
93.75% |
| V2S |
|
100.00% |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| mbx_smoke | 1 | 1 | 100.00 | |||
| mbx_smoke | 68.000s | 5010.012us | 1 | 1 | 100.00 | |
| csr_hw_reset | 1 | 1 | 100.00 | |||
| mbx_csr_hw_reset | 1.000s | 21.352us | 1 | 1 | 100.00 | |
| csr_rw | 1 | 1 | 100.00 | |||
| mbx_csr_rw | 1.000s | 21.181us | 1 | 1 | 100.00 | |
| csr_bit_bash | 1 | 1 | 100.00 | |||
| mbx_csr_bit_bash | 3.000s | 650.664us | 1 | 1 | 100.00 | |
| csr_aliasing | 1 | 1 | 100.00 | |||
| mbx_csr_aliasing | 1.000s | 18.251us | 1 | 1 | 100.00 | |
| csr_mem_rw_with_rand_reset | 1 | 1 | 100.00 | |||
| mbx_csr_mem_rw_with_rand_reset | 2.000s | 68.191us | 1 | 1 | 100.00 | |
| regwen_csr_and_corresponding_lockable_csr | 2 | 2 | 100.00 | |||
| mbx_csr_rw | 1.000s | 21.181us | 1 | 1 | 100.00 | |
| mbx_csr_aliasing | 1.000s | 18.251us | 1 | 1 | 100.00 | |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| mbx_stress | 1 | 1 | 100.00 | |||
| mbx_stress | 101.000s | 8973.978us | 1 | 1 | 100.00 | |
| mbx_max_activity | 0 | 1 | 0.00 | |||
| mbx_stress_zero_delays | 1.000s | 27.214us | 0 | 1 | 0.00 | |
| mbx_imbx_oob | 1 | 1 | 100.00 | |||
| mbx_imbx_oob | 69.000s | 3299.337us | 1 | 1 | 100.00 | |
| mbx_doe_intr_msg | 1 | 1 | 100.00 | |||
| mbx_doe_intr_msg | 16.000s | 727.957us | 1 | 1 | 100.00 | |
| alert_test | 1 | 1 | 100.00 | |||
| mbx_alert_test | 2.000s | 73.340us | 1 | 1 | 100.00 | |
| intr_test | 1 | 1 | 100.00 | |||
| mbx_intr_test | 2.000s | 80.604us | 1 | 1 | 100.00 | |
| tl_d_oob_addr_access | 1 | 1 | 100.00 | |||
| mbx_tl_errors | 5.000s | 194.357us | 1 | 1 | 100.00 | |
| tl_d_illegal_access | 1 | 1 | 100.00 | |||
| mbx_tl_errors | 5.000s | 194.357us | 1 | 1 | 100.00 | |
| tl_d_outstanding_access | 4 | 4 | 100.00 | |||
| mbx_csr_hw_reset | 1.000s | 21.352us | 1 | 1 | 100.00 | |
| mbx_csr_rw | 1.000s | 21.181us | 1 | 1 | 100.00 | |
| mbx_csr_aliasing | 1.000s | 18.251us | 1 | 1 | 100.00 | |
| mbx_same_csr_outstanding | 2.000s | 104.200us | 1 | 1 | 100.00 | |
| tl_d_partial_access | 4 | 4 | 100.00 | |||
| mbx_csr_hw_reset | 1.000s | 21.352us | 1 | 1 | 100.00 | |
| mbx_csr_rw | 1.000s | 21.181us | 1 | 1 | 100.00 | |
| mbx_csr_aliasing | 1.000s | 18.251us | 1 | 1 | 100.00 | |
| mbx_same_csr_outstanding | 2.000s | 104.200us | 1 | 1 | 100.00 | |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| tl_intg_err | 2 | 2 | 100.00 | |||
| mbx_sec_cm | 1.000s | 36.200us | 1 | 1 | 100.00 | |
| mbx_tl_intg_err | 2.000s | 86.291us | 1 | 1 | 100.00 | |