| V1 |
|
100.00% |
| V2 |
|
100.00% |
| V2S |
|
75.00% |
| V3 |
|
100.00% |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| smoke | 1 | 1 | 100.00 | |||
| rom_ctrl_smoke | 4.050s | 1875.240us | 1 | 1 | 100.00 | |
| csr_hw_reset | 1 | 1 | 100.00 | |||
| rom_ctrl_csr_hw_reset | 6.260s | 2515.216us | 1 | 1 | 100.00 | |
| csr_rw | 1 | 1 | 100.00 | |||
| rom_ctrl_csr_rw | 3.600s | 375.247us | 1 | 1 | 100.00 | |
| csr_bit_bash | 1 | 1 | 100.00 | |||
| rom_ctrl_csr_bit_bash | 4.880s | 305.087us | 1 | 1 | 100.00 | |
| csr_aliasing | 1 | 1 | 100.00 | |||
| rom_ctrl_csr_aliasing | 3.900s | 294.322us | 1 | 1 | 100.00 | |
| csr_mem_rw_with_rand_reset | 1 | 1 | 100.00 | |||
| rom_ctrl_csr_mem_rw_with_rand_reset | 4.720s | 380.986us | 1 | 1 | 100.00 | |
| regwen_csr_and_corresponding_lockable_csr | 2 | 2 | 100.00 | |||
| rom_ctrl_csr_rw | 3.600s | 375.247us | 1 | 1 | 100.00 | |
| rom_ctrl_csr_aliasing | 3.900s | 294.322us | 1 | 1 | 100.00 | |
| mem_walk | 1 | 1 | 100.00 | |||
| rom_ctrl_mem_walk | 4.220s | 128.812us | 1 | 1 | 100.00 | |
| mem_partial_access | 1 | 1 | 100.00 | |||
| rom_ctrl_mem_partial_access | 3.580s | 125.766us | 1 | 1 | 100.00 | |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| max_throughput_chk | 1 | 1 | 100.00 | |||
| rom_ctrl_max_throughput_chk | 5.580s | 303.923us | 1 | 1 | 100.00 | |
| stress_all | 1 | 1 | 100.00 | |||
| rom_ctrl_stress_all | 12.810s | 465.034us | 1 | 1 | 100.00 | |
| kmac_err_chk | 1 | 1 | 100.00 | |||
| rom_ctrl_kmac_err_chk | 7.740s | 311.227us | 1 | 1 | 100.00 | |
| alert_test | 1 | 1 | 100.00 | |||
| rom_ctrl_alert_test | 3.210s | 400.956us | 1 | 1 | 100.00 | |
| tl_d_oob_addr_access | 1 | 1 | 100.00 | |||
| rom_ctrl_tl_errors | 6.290s | 126.132us | 1 | 1 | 100.00 | |
| tl_d_illegal_access | 1 | 1 | 100.00 | |||
| rom_ctrl_tl_errors | 6.290s | 126.132us | 1 | 1 | 100.00 | |
| tl_d_outstanding_access | 4 | 4 | 100.00 | |||
| rom_ctrl_csr_hw_reset | 6.260s | 2515.216us | 1 | 1 | 100.00 | |
| rom_ctrl_csr_rw | 3.600s | 375.247us | 1 | 1 | 100.00 | |
| rom_ctrl_csr_aliasing | 3.900s | 294.322us | 1 | 1 | 100.00 | |
| rom_ctrl_same_csr_outstanding | 3.840s | 533.519us | 1 | 1 | 100.00 | |
| tl_d_partial_access | 4 | 4 | 100.00 | |||
| rom_ctrl_csr_hw_reset | 6.260s | 2515.216us | 1 | 1 | 100.00 | |
| rom_ctrl_csr_rw | 3.600s | 375.247us | 1 | 1 | 100.00 | |
| rom_ctrl_csr_aliasing | 3.900s | 294.322us | 1 | 1 | 100.00 | |
| rom_ctrl_same_csr_outstanding | 3.840s | 533.519us | 1 | 1 | 100.00 | |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| corrupt_sig_fatal_chk | 1 | 1 | 100.00 | |||
| rom_ctrl_corrupt_sig_fatal_chk | 81.980s | 5670.755us | 1 | 1 | 100.00 | |
| passthru_mem_tl_intg_err | 1 | 1 | 100.00 | |||
| rom_ctrl_passthru_mem_tl_intg_err | 14.360s | 586.543us | 1 | 1 | 100.00 | |
| tl_intg_err | 1 | 2 | 50.00 | |||
| rom_ctrl_sec_cm | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| rom_ctrl_tl_intg_err | 45.000s | 372.351us | 1 | 1 | 100.00 | |
| prim_fsm_check | 0 | 1 | 0.00 | |||
| rom_ctrl_sec_cm | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| prim_count_check | 0 | 1 | 0.00 | |||
| rom_ctrl_sec_cm | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| sec_cm_checker_ctr_consistency | 1 | 1 | 100.00 | |||
| rom_ctrl_corrupt_sig_fatal_chk | 81.980s | 5670.755us | 1 | 1 | 100.00 | |
| sec_cm_checker_ctrl_flow_consistency | 1 | 1 | 100.00 | |||
| rom_ctrl_corrupt_sig_fatal_chk | 81.980s | 5670.755us | 1 | 1 | 100.00 | |
| sec_cm_checker_fsm_local_esc | 1 | 1 | 100.00 | |||
| rom_ctrl_corrupt_sig_fatal_chk | 81.980s | 5670.755us | 1 | 1 | 100.00 | |
| sec_cm_compare_ctrl_flow_consistency | 1 | 1 | 100.00 | |||
| rom_ctrl_corrupt_sig_fatal_chk | 81.980s | 5670.755us | 1 | 1 | 100.00 | |
| sec_cm_compare_ctr_consistency | 1 | 1 | 100.00 | |||
| rom_ctrl_corrupt_sig_fatal_chk | 81.980s | 5670.755us | 1 | 1 | 100.00 | |
| sec_cm_compare_ctr_redun | 0 | 1 | 0.00 | |||
| rom_ctrl_sec_cm | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| sec_cm_fsm_sparse | 0 | 1 | 0.00 | |||
| rom_ctrl_sec_cm | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| sec_cm_mem_scramble | 1 | 1 | 100.00 | |||
| rom_ctrl_smoke | 4.050s | 1875.240us | 1 | 1 | 100.00 | |
| sec_cm_mem_digest | 1 | 1 | 100.00 | |||
| rom_ctrl_smoke | 4.050s | 1875.240us | 1 | 1 | 100.00 | |
| sec_cm_intersig_mubi | 1 | 1 | 100.00 | |||
| rom_ctrl_smoke | 4.050s | 1875.240us | 1 | 1 | 100.00 | |
| sec_cm_bus_integrity | 1 | 1 | 100.00 | |||
| rom_ctrl_tl_intg_err | 45.000s | 372.351us | 1 | 1 | 100.00 | |
| sec_cm_bus_local_esc | 2 | 2 | 100.00 | |||
| rom_ctrl_corrupt_sig_fatal_chk | 81.980s | 5670.755us | 1 | 1 | 100.00 | |
| rom_ctrl_kmac_err_chk | 7.740s | 311.227us | 1 | 1 | 100.00 | |
| sec_cm_mux_mubi | 1 | 1 | 100.00 | |||
| rom_ctrl_corrupt_sig_fatal_chk | 81.980s | 5670.755us | 1 | 1 | 100.00 | |
| sec_cm_mux_consistency | 1 | 1 | 100.00 | |||
| rom_ctrl_corrupt_sig_fatal_chk | 81.980s | 5670.755us | 1 | 1 | 100.00 | |
| sec_cm_ctrl_redun | 1 | 1 | 100.00 | |||
| rom_ctrl_corrupt_sig_fatal_chk | 81.980s | 5670.755us | 1 | 1 | 100.00 | |
| sec_cm_ctrl_mem_integrity | 1 | 1 | 100.00 | |||
| rom_ctrl_passthru_mem_tl_intg_err | 14.360s | 586.543us | 1 | 1 | 100.00 | |
| sec_cm_tlul_fifo_ctr_redun | 0 | 1 | 0.00 | |||
| rom_ctrl_sec_cm | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| stress_all_with_rand_reset | 1 | 1 | 100.00 | |||
| rom_ctrl_stress_all_with_rand_reset | 152.580s | 22440.181us | 1 | 1 | 100.00 | |