| V1 |
|
100.00% |
| V2 |
|
100.00% |
| V2S |
|
75.00% |
| V3 |
|
100.00% |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| smoke | 1 | 1 | 100.00 | |||
| rom_ctrl_smoke | 7.010s | 805.303us | 1 | 1 | 100.00 | |
| csr_hw_reset | 1 | 1 | 100.00 | |||
| rom_ctrl_csr_hw_reset | 10.450s | 290.223us | 1 | 1 | 100.00 | |
| csr_rw | 1 | 1 | 100.00 | |||
| rom_ctrl_csr_rw | 6.400s | 213.816us | 1 | 1 | 100.00 | |
| csr_bit_bash | 1 | 1 | 100.00 | |||
| rom_ctrl_csr_bit_bash | 6.110s | 630.295us | 1 | 1 | 100.00 | |
| csr_aliasing | 1 | 1 | 100.00 | |||
| rom_ctrl_csr_aliasing | 7.620s | 527.599us | 1 | 1 | 100.00 | |
| csr_mem_rw_with_rand_reset | 1 | 1 | 100.00 | |||
| rom_ctrl_csr_mem_rw_with_rand_reset | 6.400s | 850.966us | 1 | 1 | 100.00 | |
| regwen_csr_and_corresponding_lockable_csr | 2 | 2 | 100.00 | |||
| rom_ctrl_csr_rw | 6.400s | 213.816us | 1 | 1 | 100.00 | |
| rom_ctrl_csr_aliasing | 7.620s | 527.599us | 1 | 1 | 100.00 | |
| mem_walk | 1 | 1 | 100.00 | |||
| rom_ctrl_mem_walk | 6.880s | 499.015us | 1 | 1 | 100.00 | |
| mem_partial_access | 1 | 1 | 100.00 | |||
| rom_ctrl_mem_partial_access | 8.210s | 4138.512us | 1 | 1 | 100.00 | |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| max_throughput_chk | 1 | 1 | 100.00 | |||
| rom_ctrl_max_throughput_chk | 9.690s | 1102.704us | 1 | 1 | 100.00 | |
| stress_all | 1 | 1 | 100.00 | |||
| rom_ctrl_stress_all | 23.820s | 1641.911us | 1 | 1 | 100.00 | |
| kmac_err_chk | 1 | 1 | 100.00 | |||
| rom_ctrl_kmac_err_chk | 17.660s | 1079.914us | 1 | 1 | 100.00 | |
| alert_test | 1 | 1 | 100.00 | |||
| rom_ctrl_alert_test | 7.970s | 286.672us | 1 | 1 | 100.00 | |
| tl_d_oob_addr_access | 1 | 1 | 100.00 | |||
| rom_ctrl_tl_errors | 9.540s | 2511.439us | 1 | 1 | 100.00 | |
| tl_d_illegal_access | 1 | 1 | 100.00 | |||
| rom_ctrl_tl_errors | 9.540s | 2511.439us | 1 | 1 | 100.00 | |
| tl_d_outstanding_access | 4 | 4 | 100.00 | |||
| rom_ctrl_csr_hw_reset | 10.450s | 290.223us | 1 | 1 | 100.00 | |
| rom_ctrl_csr_rw | 6.400s | 213.816us | 1 | 1 | 100.00 | |
| rom_ctrl_csr_aliasing | 7.620s | 527.599us | 1 | 1 | 100.00 | |
| rom_ctrl_same_csr_outstanding | 7.030s | 1306.539us | 1 | 1 | 100.00 | |
| tl_d_partial_access | 4 | 4 | 100.00 | |||
| rom_ctrl_csr_hw_reset | 10.450s | 290.223us | 1 | 1 | 100.00 | |
| rom_ctrl_csr_rw | 6.400s | 213.816us | 1 | 1 | 100.00 | |
| rom_ctrl_csr_aliasing | 7.620s | 527.599us | 1 | 1 | 100.00 | |
| rom_ctrl_same_csr_outstanding | 7.030s | 1306.539us | 1 | 1 | 100.00 | |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| corrupt_sig_fatal_chk | 1 | 1 | 100.00 | |||
| rom_ctrl_corrupt_sig_fatal_chk | 141.620s | 15846.012us | 1 | 1 | 100.00 | |
| passthru_mem_tl_intg_err | 1 | 1 | 100.00 | |||
| rom_ctrl_passthru_mem_tl_intg_err | 55.090s | 27057.150us | 1 | 1 | 100.00 | |
| tl_intg_err | 1 | 2 | 50.00 | |||
| rom_ctrl_sec_cm | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| rom_ctrl_tl_intg_err | 101.860s | 445.280us | 1 | 1 | 100.00 | |
| prim_fsm_check | 0 | 1 | 0.00 | |||
| rom_ctrl_sec_cm | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| prim_count_check | 0 | 1 | 0.00 | |||
| rom_ctrl_sec_cm | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| sec_cm_checker_ctr_consistency | 1 | 1 | 100.00 | |||
| rom_ctrl_corrupt_sig_fatal_chk | 141.620s | 15846.012us | 1 | 1 | 100.00 | |
| sec_cm_checker_ctrl_flow_consistency | 1 | 1 | 100.00 | |||
| rom_ctrl_corrupt_sig_fatal_chk | 141.620s | 15846.012us | 1 | 1 | 100.00 | |
| sec_cm_checker_fsm_local_esc | 1 | 1 | 100.00 | |||
| rom_ctrl_corrupt_sig_fatal_chk | 141.620s | 15846.012us | 1 | 1 | 100.00 | |
| sec_cm_compare_ctrl_flow_consistency | 1 | 1 | 100.00 | |||
| rom_ctrl_corrupt_sig_fatal_chk | 141.620s | 15846.012us | 1 | 1 | 100.00 | |
| sec_cm_compare_ctr_consistency | 1 | 1 | 100.00 | |||
| rom_ctrl_corrupt_sig_fatal_chk | 141.620s | 15846.012us | 1 | 1 | 100.00 | |
| sec_cm_compare_ctr_redun | 0 | 1 | 0.00 | |||
| rom_ctrl_sec_cm | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| sec_cm_fsm_sparse | 0 | 1 | 0.00 | |||
| rom_ctrl_sec_cm | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| sec_cm_mem_scramble | 1 | 1 | 100.00 | |||
| rom_ctrl_smoke | 7.010s | 805.303us | 1 | 1 | 100.00 | |
| sec_cm_mem_digest | 1 | 1 | 100.00 | |||
| rom_ctrl_smoke | 7.010s | 805.303us | 1 | 1 | 100.00 | |
| sec_cm_intersig_mubi | 1 | 1 | 100.00 | |||
| rom_ctrl_smoke | 7.010s | 805.303us | 1 | 1 | 100.00 | |
| sec_cm_bus_integrity | 1 | 1 | 100.00 | |||
| rom_ctrl_tl_intg_err | 101.860s | 445.280us | 1 | 1 | 100.00 | |
| sec_cm_bus_local_esc | 2 | 2 | 100.00 | |||
| rom_ctrl_corrupt_sig_fatal_chk | 141.620s | 15846.012us | 1 | 1 | 100.00 | |
| rom_ctrl_kmac_err_chk | 17.660s | 1079.914us | 1 | 1 | 100.00 | |
| sec_cm_mux_mubi | 1 | 1 | 100.00 | |||
| rom_ctrl_corrupt_sig_fatal_chk | 141.620s | 15846.012us | 1 | 1 | 100.00 | |
| sec_cm_mux_consistency | 1 | 1 | 100.00 | |||
| rom_ctrl_corrupt_sig_fatal_chk | 141.620s | 15846.012us | 1 | 1 | 100.00 | |
| sec_cm_ctrl_redun | 1 | 1 | 100.00 | |||
| rom_ctrl_corrupt_sig_fatal_chk | 141.620s | 15846.012us | 1 | 1 | 100.00 | |
| sec_cm_ctrl_mem_integrity | 1 | 1 | 100.00 | |||
| rom_ctrl_passthru_mem_tl_intg_err | 55.090s | 27057.150us | 1 | 1 | 100.00 | |
| sec_cm_tlul_fifo_ctr_redun | 0 | 1 | 0.00 | |||
| rom_ctrl_sec_cm | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| stress_all_with_rand_reset | 1 | 1 | 100.00 | |||
| rom_ctrl_stress_all_with_rand_reset | 72.440s | 2848.951us | 1 | 1 | 100.00 | |