| V1 |
|
100.00% |
| V2 |
|
100.00% |
| V2S |
|
100.00% |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| smoke | 1 | 1 | 100.00 | |||
| rstmgr_smoke | 1.380s | 59.842us | 1 | 1 | 100.00 | |
| csr_hw_reset | 1 | 1 | 100.00 | |||
| rstmgr_csr_hw_reset | 1.110s | 64.421us | 1 | 1 | 100.00 | |
| csr_rw | 1 | 1 | 100.00 | |||
| rstmgr_csr_rw | 0.940s | 38.190us | 1 | 1 | 100.00 | |
| csr_bit_bash | 1 | 1 | 100.00 | |||
| rstmgr_csr_bit_bash | 2.130s | 91.032us | 1 | 1 | 100.00 | |
| csr_aliasing | 1 | 1 | 100.00 | |||
| rstmgr_csr_aliasing | 1.110s | 40.850us | 1 | 1 | 100.00 | |
| csr_mem_rw_with_rand_reset | 1 | 1 | 100.00 | |||
| rstmgr_csr_mem_rw_with_rand_reset | 1.280s | 97.767us | 1 | 1 | 100.00 | |
| regwen_csr_and_corresponding_lockable_csr | 2 | 2 | 100.00 | |||
| rstmgr_csr_rw | 0.940s | 38.190us | 1 | 1 | 100.00 | |
| rstmgr_csr_aliasing | 1.110s | 40.850us | 1 | 1 | 100.00 | |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| reset_stretcher | 1 | 1 | 100.00 | |||
| rstmgr_por_stretcher | 1.260s | 143.078us | 1 | 1 | 100.00 | |
| sw_rst | 1 | 1 | 100.00 | |||
| rstmgr_sw_rst | 1.020s | 44.337us | 1 | 1 | 100.00 | |
| sw_rst_reset_race | 1 | 1 | 100.00 | |||
| rstmgr_sw_rst_reset_race | 1.490s | 61.481us | 1 | 1 | 100.00 | |
| reset_info | 1 | 1 | 100.00 | |||
| rstmgr_reset | 6.530s | 679.844us | 1 | 1 | 100.00 | |
| cpu_info | 1 | 1 | 100.00 | |||
| rstmgr_reset | 6.530s | 679.844us | 1 | 1 | 100.00 | |
| alert_info | 1 | 1 | 100.00 | |||
| rstmgr_reset | 6.530s | 679.844us | 1 | 1 | 100.00 | |
| reset_info_capture | 1 | 1 | 100.00 | |||
| rstmgr_reset | 6.530s | 679.844us | 1 | 1 | 100.00 | |
| stress_all | 1 | 1 | 100.00 | |||
| rstmgr_stress_all | 1.910s | 169.181us | 1 | 1 | 100.00 | |
| alert_test | 1 | 1 | 100.00 | |||
| rstmgr_alert_test | 1.090s | 37.224us | 1 | 1 | 100.00 | |
| tl_d_oob_addr_access | 1 | 1 | 100.00 | |||
| rstmgr_tl_errors | 1.760s | 57.231us | 1 | 1 | 100.00 | |
| tl_d_illegal_access | 1 | 1 | 100.00 | |||
| rstmgr_tl_errors | 1.760s | 57.231us | 1 | 1 | 100.00 | |
| tl_d_outstanding_access | 4 | 4 | 100.00 | |||
| rstmgr_csr_hw_reset | 1.110s | 64.421us | 1 | 1 | 100.00 | |
| rstmgr_csr_rw | 0.940s | 38.190us | 1 | 1 | 100.00 | |
| rstmgr_csr_aliasing | 1.110s | 40.850us | 1 | 1 | 100.00 | |
| rstmgr_same_csr_outstanding | 1.180s | 40.100us | 1 | 1 | 100.00 | |
| tl_d_partial_access | 4 | 4 | 100.00 | |||
| rstmgr_csr_hw_reset | 1.110s | 64.421us | 1 | 1 | 100.00 | |
| rstmgr_csr_rw | 0.940s | 38.190us | 1 | 1 | 100.00 | |
| rstmgr_csr_aliasing | 1.110s | 40.850us | 1 | 1 | 100.00 | |
| rstmgr_same_csr_outstanding | 1.180s | 40.100us | 1 | 1 | 100.00 | |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| tl_intg_err | 2 | 2 | 100.00 | |||
| rstmgr_sec_cm | 16.380s | 3435.611us | 1 | 1 | 100.00 | |
| rstmgr_tl_intg_err | 4.070s | 633.921us | 1 | 1 | 100.00 | |
| prim_count_check | 1 | 1 | 100.00 | |||
| rstmgr_sec_cm | 16.380s | 3435.611us | 1 | 1 | 100.00 | |
| prim_fsm_check | 1 | 1 | 100.00 | |||
| rstmgr_sec_cm | 16.380s | 3435.611us | 1 | 1 | 100.00 | |
| sec_cm_bus_integrity | 1 | 1 | 100.00 | |||
| rstmgr_tl_intg_err | 4.070s | 633.921us | 1 | 1 | 100.00 | |
| sec_cm_scan_intersig_mubi | 1 | 1 | 100.00 | |||
| rstmgr_sec_cm_scan_intersig_mubi | 1.120s | 63.310us | 1 | 1 | 100.00 | |
| sec_cm_leaf_rst_bkgn_chk | 1 | 1 | 100.00 | |||
| rstmgr_leaf_rst_cnsty | 3.360s | 415.081us | 1 | 1 | 100.00 | |
| sec_cm_leaf_rst_shadow | 1 | 1 | 100.00 | |||
| rstmgr_leaf_rst_shadow_attack | 3.300s | 291.952us | 1 | 1 | 100.00 | |
| sec_cm_leaf_fsm_sparse | 1 | 1 | 100.00 | |||
| rstmgr_sec_cm | 16.380s | 3435.611us | 1 | 1 | 100.00 | |
| sec_cm_sw_rst_config_regwen | 1 | 1 | 100.00 | |||
| rstmgr_csr_rw | 0.940s | 38.190us | 1 | 1 | 100.00 | |
| sec_cm_dump_ctrl_config_regwen | 1 | 1 | 100.00 | |||
| rstmgr_csr_rw | 0.940s | 38.190us | 1 | 1 | 100.00 | |