| V1 |
|
87.10% |
| V2 |
|
60.71% |
| V2S |
|
91.67% |
| V3 |
|
0.00% |
| unmapped |
|
0.00% |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| smoke | 0 | 1 | 0.00 | |||
| rv_dm_smoke | 11.410s | 14019.275us | 0 | 1 | 0.00 | |
| jtag_dtm_csr_hw_reset | 1 | 1 | 100.00 | |||
| rv_dm_jtag_dtm_csr_hw_reset | 1.940s | 471.911us | 1 | 1 | 100.00 | |
| jtag_dtm_csr_rw | 1 | 1 | 100.00 | |||
| rv_dm_jtag_dtm_csr_rw | 2.640s | 987.474us | 1 | 1 | 100.00 | |
| jtag_dtm_csr_bit_bash | 1 | 1 | 100.00 | |||
| rv_dm_jtag_dtm_csr_bit_bash | 5.240s | 7890.468us | 1 | 1 | 100.00 | |
| jtag_dtm_csr_aliasing | 1 | 1 | 100.00 | |||
| rv_dm_jtag_dtm_csr_aliasing | 5.880s | 2422.684us | 1 | 1 | 100.00 | |
| jtag_dmi_csr_hw_reset | 1 | 1 | 100.00 | |||
| rv_dm_jtag_dmi_csr_hw_reset | 29.100s | 24419.302us | 1 | 1 | 100.00 | |
| jtag_dmi_csr_rw | 1 | 1 | 100.00 | |||
| rv_dm_jtag_dmi_csr_rw | 3.500s | 1220.259us | 1 | 1 | 100.00 | |
| jtag_dmi_csr_bit_bash | 1 | 1 | 100.00 | |||
| rv_dm_jtag_dmi_csr_bit_bash | 17.580s | 7992.834us | 1 | 1 | 100.00 | |
| jtag_dmi_csr_aliasing | 0 | 1 | 0.00 | |||
| rv_dm_jtag_dmi_csr_aliasing | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| jtag_dmi_cmderr_busy | 1 | 1 | 100.00 | |||
| rv_dm_cmderr_busy | 1.520s | 421.669us | 1 | 1 | 100.00 | |
| jtag_dmi_cmderr_not_supported | 1 | 1 | 100.00 | |||
| rv_dm_cmderr_not_supported | 1.240s | 292.995us | 1 | 1 | 100.00 | |
| cmderr_exception | 1 | 1 | 100.00 | |||
| rv_dm_cmderr_exception | 1.450s | 747.642us | 1 | 1 | 100.00 | |
| mem_tl_access_resuming | 0 | 1 | 0.00 | |||
| rv_dm_mem_tl_access_resuming | 0.920s | 154.003us | 0 | 1 | 0.00 | |
| mem_tl_access_halted | 1 | 1 | 100.00 | |||
| rv_dm_mem_tl_access_halted | 1.010s | 94.812us | 1 | 1 | 100.00 | |
| cmderr_halt_resume | 1 | 1 | 100.00 | |||
| rv_dm_cmderr_halt_resume | 1.430s | 737.334us | 1 | 1 | 100.00 | |
| dataaddr_rw_access | 1 | 1 | 100.00 | |||
| rv_dm_dataaddr_rw_access | 1.040s | 296.861us | 1 | 1 | 100.00 | |
| halt_resume | 1 | 1 | 100.00 | |||
| rv_dm_halt_resume_whereto | 3.450s | 1511.691us | 1 | 1 | 100.00 | |
| progbuf_busy | 1 | 1 | 100.00 | |||
| rv_dm_cmderr_busy | 1.520s | 421.669us | 1 | 1 | 100.00 | |
| abstractcmd_status | 1 | 1 | 100.00 | |||
| rv_dm_abstractcmd_status | 0.850s | 707.988us | 1 | 1 | 100.00 | |
| progbuf_read_write_execute | 1 | 1 | 100.00 | |||
| rv_dm_progbuf_read_write_execute | 2.180s | 855.858us | 1 | 1 | 100.00 | |
| progbuf_exception | 1 | 1 | 100.00 | |||
| rv_dm_cmderr_exception | 1.450s | 747.642us | 1 | 1 | 100.00 | |
| rom_read_access | 1 | 1 | 100.00 | |||
| rv_dm_rom_read_access | 0.940s | 217.054us | 1 | 1 | 100.00 | |
| csr_hw_reset | 1 | 1 | 100.00 | |||
| rv_dm_csr_hw_reset | 2.370s | 594.432us | 1 | 1 | 100.00 | |
| csr_rw | 1 | 1 | 100.00 | |||
| rv_dm_csr_rw | 1.630s | 109.696us | 1 | 1 | 100.00 | |
| csr_bit_bash | 1 | 1 | 100.00 | |||
| rv_dm_csr_bit_bash | 52.960s | 14651.050us | 1 | 1 | 100.00 | |
| csr_aliasing | 1 | 1 | 100.00 | |||
| rv_dm_csr_aliasing | 18.120s | 2157.972us | 1 | 1 | 100.00 | |
| csr_mem_rw_with_rand_reset | 0 | 1 | 0.00 | |||
| rv_dm_csr_mem_rw_with_rand_reset | 1.980s | 49.375us | 0 | 1 | 0.00 | |
| regwen_csr_and_corresponding_lockable_csr | 2 | 2 | 100.00 | |||
| rv_dm_csr_aliasing | 18.120s | 2157.972us | 1 | 1 | 100.00 | |
| rv_dm_csr_rw | 1.630s | 109.696us | 1 | 1 | 100.00 | |
| mem_walk | 1 | 1 | 100.00 | |||
| rv_dm_mem_walk | 1.080s | 26.757us | 1 | 1 | 100.00 | |
| mem_partial_access | 1 | 1 | 100.00 | |||
| rv_dm_mem_partial_access | 1.050s | 98.921us | 1 | 1 | 100.00 | |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| idcode | 0 | 1 | 0.00 | |||
| rv_dm_smoke | 11.410s | 14019.275us | 0 | 1 | 0.00 | |
| jtag_dtm_hard_reset | 1 | 1 | 100.00 | |||
| rv_dm_jtag_dtm_hard_reset | 0.810s | 302.178us | 1 | 1 | 100.00 | |
| jtag_dtm_idle_hint | 1 | 1 | 100.00 | |||
| rv_dm_jtag_dtm_idle_hint | 0.770s | 293.659us | 1 | 1 | 100.00 | |
| jtag_dmi_failed_op | 1 | 1 | 100.00 | |||
| rv_dm_dmi_failed_op | 0.900s | 277.601us | 1 | 1 | 100.00 | |
| jtag_dmi_dm_inactive | 1 | 1 | 100.00 | |||
| rv_dm_jtag_dmi_dm_inactive | 3.490s | 2206.712us | 1 | 1 | 100.00 | |
| sba | 0 | 2 | 0.00 | |||
| rv_dm_sba_tl_access | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| rv_dm_delayed_resp_sba_tl_access | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| bad_sba | 0 | 1 | 0.00 | |||
| rv_dm_bad_sba_tl_access | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| sba_autoincrement | 0 | 1 | 0.00 | |||
| rv_dm_autoincr_sba_tl_access | 144.040s | 300000.000us | 0 | 1 | 0.00 | |
| jtag_dmi_debug_disabled | 0 | 1 | 0.00 | |||
| rv_dm_jtag_dmi_debug_disabled | 1.120s | 314.598us | 0 | 1 | 0.00 | |
| sba_debug_disabled | 1 | 1 | 100.00 | |||
| rv_dm_sba_debug_disabled | 1.400s | 650.970us | 1 | 1 | 100.00 | |
| ndmreset_req | 1 | 1 | 100.00 | |||
| rv_dm_ndmreset_req | 1.130s | 223.156us | 1 | 1 | 100.00 | |
| hart_unavail | 0 | 1 | 0.00 | |||
| rv_dm_hart_unavail | 0.830s | 96.825us | 0 | 1 | 0.00 | |
| tap_ctrl_transitions | 1 | 2 | 50.00 | |||
| rv_dm_tap_fsm | 5.280s | 7107.396us | 1 | 1 | 100.00 | |
| rv_dm_tap_fsm_rand_reset | 0.950s | 86.710us | 0 | 1 | 0.00 | |
| hartsel_warl | 1 | 1 | 100.00 | |||
| rv_dm_hartsel_warl | 0.860s | 101.389us | 1 | 1 | 100.00 | |
| stress_all | 0 | 1 | 0.00 | |||
| rv_dm_stress_all | 0.890s | 417.934us | 0 | 1 | 0.00 | |
| alert_test | 1 | 1 | 100.00 | |||
| rv_dm_alert_test | 1.160s | 176.468us | 1 | 1 | 100.00 | |
| tl_d_oob_addr_access | 0 | 1 | 0.00 | |||
| rv_dm_tl_errors | 0.940s | 123.290us | 0 | 1 | 0.00 | |
| tl_d_illegal_access | 0 | 1 | 0.00 | |||
| rv_dm_tl_errors | 0.940s | 123.290us | 0 | 1 | 0.00 | |
| tl_d_outstanding_access | 4 | 4 | 100.00 | |||
| rv_dm_csr_aliasing | 18.120s | 2157.972us | 1 | 1 | 100.00 | |
| rv_dm_csr_hw_reset | 2.370s | 594.432us | 1 | 1 | 100.00 | |
| rv_dm_csr_rw | 1.630s | 109.696us | 1 | 1 | 100.00 | |
| rv_dm_same_csr_outstanding | 6.230s | 518.298us | 1 | 1 | 100.00 | |
| tl_d_partial_access | 4 | 4 | 100.00 | |||
| rv_dm_csr_aliasing | 18.120s | 2157.972us | 1 | 1 | 100.00 | |
| rv_dm_csr_hw_reset | 2.370s | 594.432us | 1 | 1 | 100.00 | |
| rv_dm_csr_rw | 1.630s | 109.696us | 1 | 1 | 100.00 | |
| rv_dm_same_csr_outstanding | 6.230s | 518.298us | 1 | 1 | 100.00 | |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| tl_intg_err | 2 | 2 | 100.00 | |||
| rv_dm_sec_cm | 1.430s | 366.138us | 1 | 1 | 100.00 | |
| rv_dm_tl_intg_err | 8.170s | 3534.963us | 1 | 1 | 100.00 | |
| sec_cm_bus_integrity | 1 | 1 | 100.00 | |||
| rv_dm_tl_intg_err | 8.170s | 3534.963us | 1 | 1 | 100.00 | |
| sec_cm_lc_hw_debug_en_intersig_mubi | 2 | 2 | 100.00 | |||
| rv_dm_sba_debug_disabled | 1.400s | 650.970us | 1 | 1 | 100.00 | |
| rv_dm_debug_disabled | 1.050s | 58.396us | 1 | 1 | 100.00 | |
| sec_cm_lc_dft_en_intersig_mubi | 2 | 2 | 100.00 | |||
| rv_dm_sba_debug_disabled | 1.400s | 650.970us | 1 | 1 | 100.00 | |
| rv_dm_debug_disabled | 1.050s | 58.396us | 1 | 1 | 100.00 | |
| sec_cm_otp_dis_rv_dm_late_debug_intersig_mubi | 0 | 1 | 0.00 | |||
| rv_dm_smoke | 11.410s | 14019.275us | 0 | 1 | 0.00 | |
| sec_cm_dm_en_ctrl_lc_gated | 1 | 1 | 100.00 | |||
| rv_dm_buffered_enable | 1.230s | 143.521us | 1 | 1 | 100.00 | |
| sec_cm_sba_tl_lc_gate_fsm_sparse | 1 | 1 | 100.00 | |||
| rv_dm_sparse_lc_gate_fsm | 0.900s | 90.938us | 1 | 1 | 100.00 | |
| sec_cm_mem_tl_lc_gate_fsm_sparse | 1 | 1 | 100.00 | |||
| rv_dm_sparse_lc_gate_fsm | 0.900s | 90.938us | 1 | 1 | 100.00 | |
| sec_cm_exec_ctrl_mubi | 1 | 1 | 100.00 | |||
| rv_dm_buffered_enable | 1.230s | 143.521us | 1 | 1 | 100.00 | |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| stress_all_with_rand_reset | 0 | 1 | 0.00 | |||
| rv_dm_stress_all_with_rand_reset | 0.850s | 130.134us | 0 | 1 | 0.00 | |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| Unmapped | 0 | 1 | 0.00 | |||
| rv_dm_scanmode | 0.000s | 0.000us | 0 | 1 | 0.00 | |