| V1 |
|
100.00% |
| V2 |
|
94.12% |
| V2S |
|
100.00% |
| V3 |
|
33.33% |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| random | 1 | 1 | 100.00 | |||
| rv_timer_random | 1.000s | 80.963us | 1 | 1 | 100.00 | |
| csr_hw_reset | 1 | 1 | 100.00 | |||
| rv_timer_csr_hw_reset | 0.630s | 17.677us | 1 | 1 | 100.00 | |
| csr_rw | 1 | 1 | 100.00 | |||
| rv_timer_csr_rw | 0.620s | 12.303us | 1 | 1 | 100.00 | |
| csr_bit_bash | 1 | 1 | 100.00 | |||
| rv_timer_csr_bit_bash | 2.500s | 287.932us | 1 | 1 | 100.00 | |
| csr_aliasing | 1 | 1 | 100.00 | |||
| rv_timer_csr_aliasing | 0.570s | 19.914us | 1 | 1 | 100.00 | |
| csr_mem_rw_with_rand_reset | 1 | 1 | 100.00 | |||
| rv_timer_csr_mem_rw_with_rand_reset | 0.770s | 23.549us | 1 | 1 | 100.00 | |
| regwen_csr_and_corresponding_lockable_csr | 2 | 2 | 100.00 | |||
| rv_timer_csr_rw | 0.620s | 12.303us | 1 | 1 | 100.00 | |
| rv_timer_csr_aliasing | 0.570s | 19.914us | 1 | 1 | 100.00 | |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| random_reset | 0 | 1 | 0.00 | |||
| rv_timer_random_reset | 0.740s | 347.689us | 0 | 1 | 0.00 | |
| disabled | 1 | 1 | 100.00 | |||
| rv_timer_disabled | 0.960s | 3301.884us | 1 | 1 | 100.00 | |
| cfg_update_on_fly | 1 | 1 | 100.00 | |||
| rv_timer_cfg_update_on_fly | 368.890s | 586897.933us | 1 | 1 | 100.00 | |
| no_interrupt_test | 1 | 1 | 100.00 | |||
| rv_timer_cfg_update_on_fly | 368.890s | 586897.933us | 1 | 1 | 100.00 | |
| stress | 1 | 1 | 100.00 | |||
| rv_timer_stress_all | 1.800s | 4054.738us | 1 | 1 | 100.00 | |
| alert_test | 1 | 1 | 100.00 | |||
| rv_timer_alert_test | 0.540s | 27.698us | 1 | 1 | 100.00 | |
| intr_test | 1 | 1 | 100.00 | |||
| rv_timer_intr_test | 0.650s | 16.717us | 1 | 1 | 100.00 | |
| tl_d_oob_addr_access | 1 | 1 | 100.00 | |||
| rv_timer_tl_errors | 1.920s | 1064.679us | 1 | 1 | 100.00 | |
| tl_d_illegal_access | 1 | 1 | 100.00 | |||
| rv_timer_tl_errors | 1.920s | 1064.679us | 1 | 1 | 100.00 | |
| tl_d_outstanding_access | 4 | 4 | 100.00 | |||
| rv_timer_csr_hw_reset | 0.630s | 17.677us | 1 | 1 | 100.00 | |
| rv_timer_csr_rw | 0.620s | 12.303us | 1 | 1 | 100.00 | |
| rv_timer_csr_aliasing | 0.570s | 19.914us | 1 | 1 | 100.00 | |
| rv_timer_same_csr_outstanding | 0.760s | 122.961us | 1 | 1 | 100.00 | |
| tl_d_partial_access | 4 | 4 | 100.00 | |||
| rv_timer_csr_hw_reset | 0.630s | 17.677us | 1 | 1 | 100.00 | |
| rv_timer_csr_rw | 0.620s | 12.303us | 1 | 1 | 100.00 | |
| rv_timer_csr_aliasing | 0.570s | 19.914us | 1 | 1 | 100.00 | |
| rv_timer_same_csr_outstanding | 0.760s | 122.961us | 1 | 1 | 100.00 | |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| tl_intg_err | 2 | 2 | 100.00 | |||
| rv_timer_sec_cm | 0.900s | 378.052us | 1 | 1 | 100.00 | |
| rv_timer_tl_intg_err | 1.300s | 629.472us | 1 | 1 | 100.00 | |
| sec_cm_bus_integrity | 1 | 1 | 100.00 | |||
| rv_timer_tl_intg_err | 1.300s | 629.472us | 1 | 1 | 100.00 | |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| min_value | 0 | 1 | 0.00 | |||
| rv_timer_min | 1.200s | 449.702us | 0 | 1 | 0.00 | |
| max_value | 0 | 1 | 0.00 | |||
| rv_timer_max | 0.640s | 195.459us | 0 | 1 | 0.00 | |
| stress_all_with_rand_reset | 1 | 1 | 100.00 | |||
| rv_timer_stress_all_with_rand_reset | 13.430s | 6903.323us | 1 | 1 | 100.00 | |