Simulation Results: spi_device

 
27/11/2025 16:08:38 sha: 8a15de8 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 81.13 %
  • code
  • 92.72 %
  • assert
  • 94.16 %
  • func
  • 56.50 %
  • line
  • 98.98 %
  • branch
  • 98.14 %
  • cond
  • 95.71 %
  • toggle
  • 83.54 %
  • FSM
  • 87.23 %
Validation stages
V1
100.00%
V2
96.15%
V2S
100.00%
unmapped
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
spi_device_flash_and_tpm 39.760s 45186.482us 1 1 100.00
csr_hw_reset 1 1 100.00
spi_device_csr_hw_reset 0.940s 69.301us 1 1 100.00
csr_rw 1 1 100.00
spi_device_csr_rw 1.510s 75.090us 1 1 100.00
csr_bit_bash 1 1 100.00
spi_device_csr_bit_bash 25.130s 3744.672us 1 1 100.00
csr_aliasing 1 1 100.00
spi_device_csr_aliasing 9.930s 231.416us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
spi_device_csr_mem_rw_with_rand_reset 1.380s 177.778us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
spi_device_csr_rw 1.510s 75.090us 1 1 100.00
spi_device_csr_aliasing 9.930s 231.416us 1 1 100.00
mem_walk 1 1 100.00
spi_device_mem_walk 0.690s 13.318us 1 1 100.00
mem_partial_access 1 1 100.00
spi_device_mem_partial_access 1.090s 19.171us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
csb_read 1 1 100.00
spi_device_csb_read 0.780s 16.327us 1 1 100.00
mem_parity 0 1 0.00
spi_device_mem_parity 0.720s 5.251us 0 1 0.00
mem_cfg 0 1 0.00
spi_device_ram_cfg 0.690s 3.383us 0 1 0.00
tpm_read 1 1 100.00
spi_device_tpm_rw 1.020s 65.366us 1 1 100.00
tpm_write 1 1 100.00
spi_device_tpm_rw 1.020s 65.366us 1 1 100.00
tpm_hw_reg 2 2 100.00
spi_device_tpm_read_hw_reg 11.990s 11166.996us 1 1 100.00
spi_device_tpm_sts_read 1.000s 33.475us 1 1 100.00
tpm_fully_random_case 1 1 100.00
spi_device_tpm_all 8.480s 1177.387us 1 1 100.00
pass_cmd_filtering 2 2 100.00
spi_device_pass_cmd_filtering 9.960s 8258.795us 1 1 100.00
spi_device_flash_all 31.610s 6607.004us 1 1 100.00
pass_addr_translation 2 2 100.00
spi_device_pass_addr_payload_swap 3.960s 3836.791us 1 1 100.00
spi_device_flash_all 31.610s 6607.004us 1 1 100.00
pass_payload_translation 2 2 100.00
spi_device_pass_addr_payload_swap 3.960s 3836.791us 1 1 100.00
spi_device_flash_all 31.610s 6607.004us 1 1 100.00
cmd_info_slots 1 1 100.00
spi_device_flash_all 31.610s 6607.004us 1 1 100.00
cmd_read_status 2 2 100.00
spi_device_intercept 2.170s 159.898us 1 1 100.00
spi_device_flash_all 31.610s 6607.004us 1 1 100.00
cmd_read_jedec 2 2 100.00
spi_device_intercept 2.170s 159.898us 1 1 100.00
spi_device_flash_all 31.610s 6607.004us 1 1 100.00
cmd_read_sfdp 2 2 100.00
spi_device_intercept 2.170s 159.898us 1 1 100.00
spi_device_flash_all 31.610s 6607.004us 1 1 100.00
cmd_fast_read 2 2 100.00
spi_device_intercept 2.170s 159.898us 1 1 100.00
spi_device_flash_all 31.610s 6607.004us 1 1 100.00
cmd_read_pipeline 2 2 100.00
spi_device_intercept 2.170s 159.898us 1 1 100.00
spi_device_flash_all 31.610s 6607.004us 1 1 100.00
flash_cmd_upload 1 1 100.00
spi_device_upload 5.750s 1827.599us 1 1 100.00
mailbox_command 1 1 100.00
spi_device_mailbox 16.570s 3714.982us 1 1 100.00
mailbox_cross_outside_command 1 1 100.00
spi_device_mailbox 16.570s 3714.982us 1 1 100.00
mailbox_cross_inside_command 1 1 100.00
spi_device_mailbox 16.570s 3714.982us 1 1 100.00
cmd_read_buffer 2 2 100.00
spi_device_flash_mode 6.330s 2121.267us 1 1 100.00
spi_device_read_buffer_direct 7.620s 1194.317us 1 1 100.00
cmd_dummy_cycle 2 2 100.00
spi_device_mailbox 16.570s 3714.982us 1 1 100.00
spi_device_flash_all 31.610s 6607.004us 1 1 100.00
quad_spi 1 1 100.00
spi_device_flash_all 31.610s 6607.004us 1 1 100.00
dual_spi 1 1 100.00
spi_device_flash_all 31.610s 6607.004us 1 1 100.00
4b_3b_feature 1 1 100.00
spi_device_cfg_cmd 3.770s 596.507us 1 1 100.00
write_enable_disable 1 1 100.00
spi_device_cfg_cmd 3.770s 596.507us 1 1 100.00
TPM_with_flash_or_passthrough_mode 1 1 100.00
spi_device_flash_and_tpm 39.760s 45186.482us 1 1 100.00
tpm_and_flash_trans_with_min_inactive_time 1 1 100.00
spi_device_flash_and_tpm_min_idle 47.540s 38150.803us 1 1 100.00
stress_all 1 1 100.00
spi_device_stress_all 1.050s 67.452us 1 1 100.00
alert_test 1 1 100.00
spi_device_alert_test 0.750s 45.199us 1 1 100.00
intr_test 1 1 100.00
spi_device_intr_test 0.670s 11.962us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
spi_device_tl_errors 1.670s 141.037us 1 1 100.00
tl_d_illegal_access 1 1 100.00
spi_device_tl_errors 1.670s 141.037us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
spi_device_csr_hw_reset 0.940s 69.301us 1 1 100.00
spi_device_csr_rw 1.510s 75.090us 1 1 100.00
spi_device_csr_aliasing 9.930s 231.416us 1 1 100.00
spi_device_same_csr_outstanding 1.620s 144.256us 1 1 100.00
tl_d_partial_access 4 4 100.00
spi_device_csr_hw_reset 0.940s 69.301us 1 1 100.00
spi_device_csr_rw 1.510s 75.090us 1 1 100.00
spi_device_csr_aliasing 9.930s 231.416us 1 1 100.00
spi_device_same_csr_outstanding 1.620s 144.256us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
spi_device_tl_intg_err 4.670s 425.954us 1 1 100.00
spi_device_sec_cm 0.920s 304.874us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
spi_device_tl_intg_err 4.670s 425.954us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
Unmapped 1 1 100.00
spi_device_flash_mode_ignore_cmds 49.700s 103160.213us 1 1 100.00