| V1 |
|
100.00% |
| V2 |
|
96.00% |
| V2S |
|
75.00% |
| V3 |
|
100.00% |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| smoke | 1 | 1 | 100.00 | |||
| sram_ctrl_smoke | 3.580s | 3457.236us | 1 | 1 | 100.00 | |
| csr_hw_reset | 1 | 1 | 100.00 | |||
| sram_ctrl_csr_hw_reset | 0.620s | 32.337us | 1 | 1 | 100.00 | |
| csr_rw | 1 | 1 | 100.00 | |||
| sram_ctrl_csr_rw | 0.660s | 15.720us | 1 | 1 | 100.00 | |
| csr_bit_bash | 1 | 1 | 100.00 | |||
| sram_ctrl_csr_bit_bash | 1.160s | 84.225us | 1 | 1 | 100.00 | |
| csr_aliasing | 1 | 1 | 100.00 | |||
| sram_ctrl_csr_aliasing | 0.740s | 18.426us | 1 | 1 | 100.00 | |
| csr_mem_rw_with_rand_reset | 1 | 1 | 100.00 | |||
| sram_ctrl_csr_mem_rw_with_rand_reset | 2.210s | 949.371us | 1 | 1 | 100.00 | |
| regwen_csr_and_corresponding_lockable_csr | 2 | 2 | 100.00 | |||
| sram_ctrl_csr_rw | 0.660s | 15.720us | 1 | 1 | 100.00 | |
| sram_ctrl_csr_aliasing | 0.740s | 18.426us | 1 | 1 | 100.00 | |
| mem_walk | 1 | 1 | 100.00 | |||
| sram_ctrl_mem_walk | 109.810s | 34575.169us | 1 | 1 | 100.00 | |
| mem_partial_access | 1 | 1 | 100.00 | |||
| sram_ctrl_mem_partial_access | 109.020s | 19939.643us | 1 | 1 | 100.00 | |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| multiple_keys | 1 | 1 | 100.00 | |||
| sram_ctrl_multiple_keys | 184.490s | 19938.039us | 1 | 1 | 100.00 | |
| stress_pipeline | 1 | 1 | 100.00 | |||
| sram_ctrl_stress_pipeline | 275.200s | 98836.069us | 1 | 1 | 100.00 | |
| bijection | 0 | 1 | 0.00 | |||
| sram_ctrl_bijection | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| access_during_key_req | 1 | 1 | 100.00 | |||
| sram_ctrl_access_during_key_req | 805.390s | 292468.589us | 1 | 1 | 100.00 | |
| lc_escalation | 1 | 1 | 100.00 | |||
| sram_ctrl_lc_escalation | 30.000s | 31226.855us | 1 | 1 | 100.00 | |
| executable | 1 | 1 | 100.00 | |||
| sram_ctrl_executable | 562.960s | 65879.277us | 1 | 1 | 100.00 | |
| partial_access | 2 | 2 | 100.00 | |||
| sram_ctrl_partial_access | 9.130s | 1182.157us | 1 | 1 | 100.00 | |
| sram_ctrl_partial_access_b2b | 352.940s | 18840.264us | 1 | 1 | 100.00 | |
| max_throughput | 3 | 3 | 100.00 | |||
| sram_ctrl_max_throughput | 40.760s | 825.047us | 1 | 1 | 100.00 | |
| sram_ctrl_throughput_w_partial_write | 26.580s | 803.355us | 1 | 1 | 100.00 | |
| sram_ctrl_throughput_w_readback | 28.140s | 1695.486us | 1 | 1 | 100.00 | |
| regwen | 1 | 1 | 100.00 | |||
| sram_ctrl_regwen | 627.090s | 101581.266us | 1 | 1 | 100.00 | |
| ram_cfg | 1 | 1 | 100.00 | |||
| sram_ctrl_ram_cfg | 2.330s | 1243.144us | 1 | 1 | 100.00 | |
| stress_all | 1 | 1 | 100.00 | |||
| sram_ctrl_stress_all | 740.660s | 119749.049us | 1 | 1 | 100.00 | |
| alert_test | 1 | 1 | 100.00 | |||
| sram_ctrl_alert_test | 0.620s | 15.282us | 1 | 1 | 100.00 | |
| tl_d_oob_addr_access | 1 | 1 | 100.00 | |||
| sram_ctrl_tl_errors | 1.810s | 267.213us | 1 | 1 | 100.00 | |
| tl_d_illegal_access | 1 | 1 | 100.00 | |||
| sram_ctrl_tl_errors | 1.810s | 267.213us | 1 | 1 | 100.00 | |
| tl_d_outstanding_access | 4 | 4 | 100.00 | |||
| sram_ctrl_csr_hw_reset | 0.620s | 32.337us | 1 | 1 | 100.00 | |
| sram_ctrl_csr_rw | 0.660s | 15.720us | 1 | 1 | 100.00 | |
| sram_ctrl_csr_aliasing | 0.740s | 18.426us | 1 | 1 | 100.00 | |
| sram_ctrl_same_csr_outstanding | 0.690s | 148.412us | 1 | 1 | 100.00 | |
| tl_d_partial_access | 4 | 4 | 100.00 | |||
| sram_ctrl_csr_hw_reset | 0.620s | 32.337us | 1 | 1 | 100.00 | |
| sram_ctrl_csr_rw | 0.660s | 15.720us | 1 | 1 | 100.00 | |
| sram_ctrl_csr_aliasing | 0.740s | 18.426us | 1 | 1 | 100.00 | |
| sram_ctrl_same_csr_outstanding | 0.690s | 148.412us | 1 | 1 | 100.00 | |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| passthru_mem_tl_intg_err | 1 | 1 | 100.00 | |||
| sram_ctrl_passthru_mem_tl_intg_err | 15.050s | 10827.790us | 1 | 1 | 100.00 | |
| tl_intg_err | 1 | 2 | 50.00 | |||
| sram_ctrl_sec_cm | 0.580s | 10.892us | 0 | 1 | 0.00 | |
| sram_ctrl_tl_intg_err | 1.880s | 291.911us | 1 | 1 | 100.00 | |
| prim_count_check | 0 | 1 | 0.00 | |||
| sram_ctrl_sec_cm | 0.580s | 10.892us | 0 | 1 | 0.00 | |
| sec_cm_bus_integrity | 1 | 1 | 100.00 | |||
| sram_ctrl_tl_intg_err | 1.880s | 291.911us | 1 | 1 | 100.00 | |
| sec_cm_ctrl_config_regwen | 1 | 1 | 100.00 | |||
| sram_ctrl_regwen | 627.090s | 101581.266us | 1 | 1 | 100.00 | |
| sec_cm_readback_config_regwen | 1 | 1 | 100.00 | |||
| sram_ctrl_regwen | 627.090s | 101581.266us | 1 | 1 | 100.00 | |
| sec_cm_exec_config_regwen | 1 | 1 | 100.00 | |||
| sram_ctrl_csr_rw | 0.660s | 15.720us | 1 | 1 | 100.00 | |
| sec_cm_exec_config_mubi | 1 | 1 | 100.00 | |||
| sram_ctrl_executable | 562.960s | 65879.277us | 1 | 1 | 100.00 | |
| sec_cm_exec_intersig_mubi | 1 | 1 | 100.00 | |||
| sram_ctrl_executable | 562.960s | 65879.277us | 1 | 1 | 100.00 | |
| sec_cm_lc_hw_debug_en_intersig_mubi | 1 | 1 | 100.00 | |||
| sram_ctrl_executable | 562.960s | 65879.277us | 1 | 1 | 100.00 | |
| sec_cm_lc_escalate_en_intersig_mubi | 1 | 1 | 100.00 | |||
| sram_ctrl_lc_escalation | 30.000s | 31226.855us | 1 | 1 | 100.00 | |
| sec_cm_prim_ram_ctrl_mubi | 1 | 1 | 100.00 | |||
| sram_ctrl_mubi_enc_err | 3.750s | 1286.434us | 1 | 1 | 100.00 | |
| sec_cm_mem_integrity | 1 | 1 | 100.00 | |||
| sram_ctrl_passthru_mem_tl_intg_err | 15.050s | 10827.790us | 1 | 1 | 100.00 | |
| sec_cm_mem_readback | 1 | 1 | 100.00 | |||
| sram_ctrl_readback_err | 3.500s | 7348.376us | 1 | 1 | 100.00 | |
| sec_cm_mem_scramble | 1 | 1 | 100.00 | |||
| sram_ctrl_smoke | 3.580s | 3457.236us | 1 | 1 | 100.00 | |
| sec_cm_addr_scramble | 1 | 1 | 100.00 | |||
| sram_ctrl_smoke | 3.580s | 3457.236us | 1 | 1 | 100.00 | |
| sec_cm_instr_bus_lc_gated | 1 | 1 | 100.00 | |||
| sram_ctrl_executable | 562.960s | 65879.277us | 1 | 1 | 100.00 | |
| sec_cm_ram_tl_lc_gate_fsm_sparse | 0 | 1 | 0.00 | |||
| sram_ctrl_sec_cm | 0.580s | 10.892us | 0 | 1 | 0.00 | |
| sec_cm_key_global_esc | 1 | 1 | 100.00 | |||
| sram_ctrl_lc_escalation | 30.000s | 31226.855us | 1 | 1 | 100.00 | |
| sec_cm_key_local_esc | 0 | 1 | 0.00 | |||
| sram_ctrl_sec_cm | 0.580s | 10.892us | 0 | 1 | 0.00 | |
| sec_cm_init_ctr_redun | 0 | 1 | 0.00 | |||
| sram_ctrl_sec_cm | 0.580s | 10.892us | 0 | 1 | 0.00 | |
| sec_cm_scramble_key_sideload | 1 | 1 | 100.00 | |||
| sram_ctrl_smoke | 3.580s | 3457.236us | 1 | 1 | 100.00 | |
| sec_cm_tlul_fifo_ctr_redun | 0 | 1 | 0.00 | |||
| sram_ctrl_sec_cm | 0.580s | 10.892us | 0 | 1 | 0.00 | |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| stress_all_with_rand_reset | 1 | 1 | 100.00 | |||
| sram_ctrl_stress_all_with_rand_reset | 43.230s | 2628.582us | 1 | 1 | 100.00 | |