| V1 |
|
100.00% |
| V2 |
|
96.00% |
| V2S |
|
75.00% |
| V3 |
|
100.00% |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| smoke | 1 | 1 | 100.00 | |||
| sram_ctrl_smoke | 8.910s | 436.933us | 1 | 1 | 100.00 | |
| csr_hw_reset | 1 | 1 | 100.00 | |||
| sram_ctrl_csr_hw_reset | 0.720s | 37.676us | 1 | 1 | 100.00 | |
| csr_rw | 1 | 1 | 100.00 | |||
| sram_ctrl_csr_rw | 0.650s | 17.601us | 1 | 1 | 100.00 | |
| csr_bit_bash | 1 | 1 | 100.00 | |||
| sram_ctrl_csr_bit_bash | 1.650s | 179.931us | 1 | 1 | 100.00 | |
| csr_aliasing | 1 | 1 | 100.00 | |||
| sram_ctrl_csr_aliasing | 0.630s | 15.133us | 1 | 1 | 100.00 | |
| csr_mem_rw_with_rand_reset | 1 | 1 | 100.00 | |||
| sram_ctrl_csr_mem_rw_with_rand_reset | 1.610s | 72.929us | 1 | 1 | 100.00 | |
| regwen_csr_and_corresponding_lockable_csr | 2 | 2 | 100.00 | |||
| sram_ctrl_csr_rw | 0.650s | 17.601us | 1 | 1 | 100.00 | |
| sram_ctrl_csr_aliasing | 0.630s | 15.133us | 1 | 1 | 100.00 | |
| mem_walk | 1 | 1 | 100.00 | |||
| sram_ctrl_mem_walk | 7.640s | 687.884us | 1 | 1 | 100.00 | |
| mem_partial_access | 1 | 1 | 100.00 | |||
| sram_ctrl_mem_partial_access | 3.430s | 526.790us | 1 | 1 | 100.00 | |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| multiple_keys | 1 | 1 | 100.00 | |||
| sram_ctrl_multiple_keys | 484.350s | 32129.386us | 1 | 1 | 100.00 | |
| stress_pipeline | 1 | 1 | 100.00 | |||
| sram_ctrl_stress_pipeline | 103.800s | 5439.105us | 1 | 1 | 100.00 | |
| bijection | 1 | 1 | 100.00 | |||
| sram_ctrl_bijection | 9.800s | 234.862us | 1 | 1 | 100.00 | |
| access_during_key_req | 1 | 1 | 100.00 | |||
| sram_ctrl_access_during_key_req | 34.060s | 303.101us | 1 | 1 | 100.00 | |
| lc_escalation | 1 | 1 | 100.00 | |||
| sram_ctrl_lc_escalation | 2.510s | 323.845us | 1 | 1 | 100.00 | |
| executable | 1 | 1 | 100.00 | |||
| sram_ctrl_executable | 399.170s | 60860.132us | 1 | 1 | 100.00 | |
| partial_access | 2 | 2 | 100.00 | |||
| sram_ctrl_partial_access | 1.940s | 159.776us | 1 | 1 | 100.00 | |
| sram_ctrl_partial_access_b2b | 250.080s | 48041.781us | 1 | 1 | 100.00 | |
| max_throughput | 3 | 3 | 100.00 | |||
| sram_ctrl_max_throughput | 22.120s | 116.350us | 1 | 1 | 100.00 | |
| sram_ctrl_throughput_w_partial_write | 5.070s | 98.165us | 1 | 1 | 100.00 | |
| sram_ctrl_throughput_w_readback | 14.830s | 686.029us | 1 | 1 | 100.00 | |
| regwen | 1 | 1 | 100.00 | |||
| sram_ctrl_regwen | 319.030s | 13022.075us | 1 | 1 | 100.00 | |
| ram_cfg | 1 | 1 | 100.00 | |||
| sram_ctrl_ram_cfg | 0.710s | 25.649us | 1 | 1 | 100.00 | |
| stress_all | 0 | 1 | 0.00 | |||
| sram_ctrl_stress_all | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| alert_test | 1 | 1 | 100.00 | |||
| sram_ctrl_alert_test | 0.610s | 33.883us | 1 | 1 | 100.00 | |
| tl_d_oob_addr_access | 1 | 1 | 100.00 | |||
| sram_ctrl_tl_errors | 2.110s | 34.195us | 1 | 1 | 100.00 | |
| tl_d_illegal_access | 1 | 1 | 100.00 | |||
| sram_ctrl_tl_errors | 2.110s | 34.195us | 1 | 1 | 100.00 | |
| tl_d_outstanding_access | 4 | 4 | 100.00 | |||
| sram_ctrl_csr_hw_reset | 0.720s | 37.676us | 1 | 1 | 100.00 | |
| sram_ctrl_csr_rw | 0.650s | 17.601us | 1 | 1 | 100.00 | |
| sram_ctrl_csr_aliasing | 0.630s | 15.133us | 1 | 1 | 100.00 | |
| sram_ctrl_same_csr_outstanding | 0.680s | 48.384us | 1 | 1 | 100.00 | |
| tl_d_partial_access | 4 | 4 | 100.00 | |||
| sram_ctrl_csr_hw_reset | 0.720s | 37.676us | 1 | 1 | 100.00 | |
| sram_ctrl_csr_rw | 0.650s | 17.601us | 1 | 1 | 100.00 | |
| sram_ctrl_csr_aliasing | 0.630s | 15.133us | 1 | 1 | 100.00 | |
| sram_ctrl_same_csr_outstanding | 0.680s | 48.384us | 1 | 1 | 100.00 | |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| passthru_mem_tl_intg_err | 1 | 1 | 100.00 | |||
| sram_ctrl_passthru_mem_tl_intg_err | 2.610s | 1218.339us | 1 | 1 | 100.00 | |
| tl_intg_err | 1 | 2 | 50.00 | |||
| sram_ctrl_sec_cm | 0.740s | 12.605us | 0 | 1 | 0.00 | |
| sram_ctrl_tl_intg_err | 1.810s | 249.007us | 1 | 1 | 100.00 | |
| prim_count_check | 0 | 1 | 0.00 | |||
| sram_ctrl_sec_cm | 0.740s | 12.605us | 0 | 1 | 0.00 | |
| sec_cm_bus_integrity | 1 | 1 | 100.00 | |||
| sram_ctrl_tl_intg_err | 1.810s | 249.007us | 1 | 1 | 100.00 | |
| sec_cm_ctrl_config_regwen | 1 | 1 | 100.00 | |||
| sram_ctrl_regwen | 319.030s | 13022.075us | 1 | 1 | 100.00 | |
| sec_cm_readback_config_regwen | 1 | 1 | 100.00 | |||
| sram_ctrl_regwen | 319.030s | 13022.075us | 1 | 1 | 100.00 | |
| sec_cm_exec_config_regwen | 1 | 1 | 100.00 | |||
| sram_ctrl_csr_rw | 0.650s | 17.601us | 1 | 1 | 100.00 | |
| sec_cm_exec_config_mubi | 1 | 1 | 100.00 | |||
| sram_ctrl_executable | 399.170s | 60860.132us | 1 | 1 | 100.00 | |
| sec_cm_exec_intersig_mubi | 1 | 1 | 100.00 | |||
| sram_ctrl_executable | 399.170s | 60860.132us | 1 | 1 | 100.00 | |
| sec_cm_lc_hw_debug_en_intersig_mubi | 1 | 1 | 100.00 | |||
| sram_ctrl_executable | 399.170s | 60860.132us | 1 | 1 | 100.00 | |
| sec_cm_lc_escalate_en_intersig_mubi | 1 | 1 | 100.00 | |||
| sram_ctrl_lc_escalation | 2.510s | 323.845us | 1 | 1 | 100.00 | |
| sec_cm_prim_ram_ctrl_mubi | 1 | 1 | 100.00 | |||
| sram_ctrl_mubi_enc_err | 0.940s | 95.596us | 1 | 1 | 100.00 | |
| sec_cm_mem_integrity | 1 | 1 | 100.00 | |||
| sram_ctrl_passthru_mem_tl_intg_err | 2.610s | 1218.339us | 1 | 1 | 100.00 | |
| sec_cm_mem_readback | 1 | 1 | 100.00 | |||
| sram_ctrl_readback_err | 0.920s | 518.843us | 1 | 1 | 100.00 | |
| sec_cm_mem_scramble | 1 | 1 | 100.00 | |||
| sram_ctrl_smoke | 8.910s | 436.933us | 1 | 1 | 100.00 | |
| sec_cm_addr_scramble | 1 | 1 | 100.00 | |||
| sram_ctrl_smoke | 8.910s | 436.933us | 1 | 1 | 100.00 | |
| sec_cm_instr_bus_lc_gated | 1 | 1 | 100.00 | |||
| sram_ctrl_executable | 399.170s | 60860.132us | 1 | 1 | 100.00 | |
| sec_cm_ram_tl_lc_gate_fsm_sparse | 0 | 1 | 0.00 | |||
| sram_ctrl_sec_cm | 0.740s | 12.605us | 0 | 1 | 0.00 | |
| sec_cm_key_global_esc | 1 | 1 | 100.00 | |||
| sram_ctrl_lc_escalation | 2.510s | 323.845us | 1 | 1 | 100.00 | |
| sec_cm_key_local_esc | 0 | 1 | 0.00 | |||
| sram_ctrl_sec_cm | 0.740s | 12.605us | 0 | 1 | 0.00 | |
| sec_cm_init_ctr_redun | 0 | 1 | 0.00 | |||
| sram_ctrl_sec_cm | 0.740s | 12.605us | 0 | 1 | 0.00 | |
| sec_cm_scramble_key_sideload | 1 | 1 | 100.00 | |||
| sram_ctrl_smoke | 8.910s | 436.933us | 1 | 1 | 100.00 | |
| sec_cm_tlul_fifo_ctr_redun | 0 | 1 | 0.00 | |||
| sram_ctrl_sec_cm | 0.740s | 12.605us | 0 | 1 | 0.00 | |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| stress_all_with_rand_reset | 1 | 1 | 100.00 | |||
| sram_ctrl_stress_all_with_rand_reset | 69.570s | 2831.201us | 1 | 1 | 100.00 | |