Simulation Results: uart

 
27/11/2025 16:08:38 sha: 8a15de8 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 84.15 %
  • code
  • 95.90 %
  • assert
  • 96.83 %
  • func
  • 59.73 %
  • line
  • 99.17 %
  • branch
  • 97.44 %
  • cond
  • 95.45 %
  • toggle
  • 91.55 %
Validation stages
V1
100.00%
V2
97.06%
V2S
100.00%
V3
0.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
uart_smoke 8.240s 5380.755us 1 1 100.00
csr_hw_reset 1 1 100.00
uart_csr_hw_reset 0.590s 140.635us 1 1 100.00
csr_rw 1 1 100.00
uart_csr_rw 0.590s 16.859us 1 1 100.00
csr_bit_bash 1 1 100.00
uart_csr_bit_bash 1.090s 33.652us 1 1 100.00
csr_aliasing 1 1 100.00
uart_csr_aliasing 0.690s 43.073us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
uart_csr_mem_rw_with_rand_reset 0.690s 24.759us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
uart_csr_rw 0.590s 16.859us 1 1 100.00
uart_csr_aliasing 0.690s 43.073us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
base_random_seq 1 1 100.00
uart_tx_rx 12.040s 138722.320us 1 1 100.00
parity 2 2 100.00
uart_smoke 8.240s 5380.755us 1 1 100.00
uart_tx_rx 12.040s 138722.320us 1 1 100.00
parity_error 2 2 100.00
uart_intr 278.850s 614041.431us 1 1 100.00
uart_rx_parity_err 176.580s 145538.198us 1 1 100.00
watermark 2 2 100.00
uart_tx_rx 12.040s 138722.320us 1 1 100.00
uart_intr 278.850s 614041.431us 1 1 100.00
fifo_full 1 1 100.00
uart_fifo_full 51.240s 190324.907us 1 1 100.00
fifo_overflow 1 1 100.00
uart_fifo_overflow 79.930s 72133.792us 1 1 100.00
fifo_reset 1 1 100.00
uart_fifo_reset 47.420s 59075.191us 1 1 100.00
rx_frame_err 1 1 100.00
uart_intr 278.850s 614041.431us 1 1 100.00
rx_break_err 1 1 100.00
uart_intr 278.850s 614041.431us 1 1 100.00
rx_timeout 1 1 100.00
uart_intr 278.850s 614041.431us 1 1 100.00
perf 1 1 100.00
uart_perf 220.330s 14470.600us 1 1 100.00
sys_loopback 1 1 100.00
uart_loopback 0.830s 2463.674us 1 1 100.00
line_loopback 1 1 100.00
uart_loopback 0.830s 2463.674us 1 1 100.00
rx_noise_filter 0 1 0.00
uart_noise_filter 27.400s 44845.514us 0 1 0.00
rx_start_bit_filter 1 1 100.00
uart_rx_start_bit_filter 16.570s 34756.342us 1 1 100.00
tx_overide 1 1 100.00
uart_tx_ovrd 1.420s 927.479us 1 1 100.00
rx_oversample 1 1 100.00
uart_rx_oversample 3.550s 1356.294us 1 1 100.00
long_b2b_transfer 1 1 100.00
uart_long_xfer_wo_dly 65.450s 69243.127us 1 1 100.00
stress_all 1 1 100.00
uart_stress_all 675.640s 295737.723us 1 1 100.00
alert_test 1 1 100.00
uart_alert_test 0.560s 79.354us 1 1 100.00
intr_test 1 1 100.00
uart_intr_test 0.670s 51.131us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
uart_tl_errors 0.830s 175.348us 1 1 100.00
tl_d_illegal_access 1 1 100.00
uart_tl_errors 0.830s 175.348us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
uart_csr_hw_reset 0.590s 140.635us 1 1 100.00
uart_csr_rw 0.590s 16.859us 1 1 100.00
uart_csr_aliasing 0.690s 43.073us 1 1 100.00
uart_same_csr_outstanding 0.720s 19.250us 1 1 100.00
tl_d_partial_access 4 4 100.00
uart_csr_hw_reset 0.590s 140.635us 1 1 100.00
uart_csr_rw 0.590s 16.859us 1 1 100.00
uart_csr_aliasing 0.690s 43.073us 1 1 100.00
uart_same_csr_outstanding 0.720s 19.250us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
uart_sec_cm 0.750s 199.033us 1 1 100.00
uart_tl_intg_err 1.180s 94.798us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
uart_tl_intg_err 1.180s 94.798us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 0 1 0.00
uart_stress_all_with_rand_reset 7.320s 2671.548us 0 1 0.00