Simulation Results: clkmgr

 
01/12/2025 16:07:45 sha: a49b553 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 78.21 %
  • code
  • 70.01 %
  • assert
  • 90.08 %
  • func
  • 74.53 %
  • line
  • 82.50 %
  • branch
  • 87.58 %
  • cond
  • 80.56 %
  • toggle
  • 99.43 %
  • FSM
  • 0.00 %
Validation stages
V1
87.50%
V2
68.42%
V2S
70.59%
V3
0.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
clkmgr_smoke 2.240s 203.773us 1 1 100.00
csr_hw_reset 1 1 100.00
clkmgr_csr_hw_reset 0.970s 44.876us 1 1 100.00
csr_rw 1 1 100.00
clkmgr_csr_rw 0.850s 18.558us 1 1 100.00
csr_bit_bash 0 1 0.00
clkmgr_csr_bit_bash 0.580s 2.013us 0 1 0.00
csr_aliasing 1 1 100.00
clkmgr_csr_aliasing 0.840s 18.400us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
clkmgr_csr_mem_rw_with_rand_reset 1.410s 28.622us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
clkmgr_csr_rw 0.850s 18.558us 1 1 100.00
clkmgr_csr_aliasing 0.840s 18.400us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
peri_enables 1 1 100.00
clkmgr_peri 0.900s 14.347us 1 1 100.00
trans_enables 1 1 100.00
clkmgr_trans 1.750s 130.406us 1 1 100.00
clk_status 1 1 100.00
clkmgr_clk_status 0.860s 27.312us 1 1 100.00
jitter 1 1 100.00
clkmgr_smoke 2.240s 203.773us 1 1 100.00
frequency 0 1 0.00
clkmgr_frequency 0.850s 7.604us 0 1 0.00
frequency_timeout 0 1 0.00
clkmgr_frequency_timeout 0.610s 4.791us 0 1 0.00
frequency_overflow 0 1 0.00
clkmgr_frequency 0.850s 7.604us 0 1 0.00
stress_all 0 1 0.00
clkmgr_stress_all 0.900s 11.428us 0 1 0.00
alert_test 1 1 100.00
clkmgr_alert_test 1.550s 127.035us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
clkmgr_tl_errors 2.830s 133.300us 1 1 100.00
tl_d_illegal_access 1 1 100.00
clkmgr_tl_errors 2.830s 133.300us 1 1 100.00
tl_d_outstanding_access 3 4 75.00
clkmgr_csr_hw_reset 0.970s 44.876us 1 1 100.00
clkmgr_csr_rw 0.850s 18.558us 1 1 100.00
clkmgr_csr_aliasing 0.840s 18.400us 1 1 100.00
clkmgr_same_csr_outstanding 0.620s 5.384us 0 1 0.00
tl_d_partial_access 3 4 75.00
clkmgr_csr_hw_reset 0.970s 44.876us 1 1 100.00
clkmgr_csr_rw 0.850s 18.558us 1 1 100.00
clkmgr_csr_aliasing 0.840s 18.400us 1 1 100.00
clkmgr_same_csr_outstanding 0.620s 5.384us 0 1 0.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 1 2 50.00
clkmgr_sec_cm 5.440s 582.891us 1 1 100.00
clkmgr_tl_intg_err 0.850s 9.556us 0 1 0.00
shadow_reg_update_error 1 1 100.00
clkmgr_shadow_reg_errors 1.260s 62.287us 1 1 100.00
shadow_reg_read_clear_staged_value 1 1 100.00
clkmgr_shadow_reg_errors 1.260s 62.287us 1 1 100.00
shadow_reg_storage_error 1 1 100.00
clkmgr_shadow_reg_errors 1.260s 62.287us 1 1 100.00
shadowed_reset_glitch 1 1 100.00
clkmgr_shadow_reg_errors 1.260s 62.287us 1 1 100.00
shadow_reg_update_error_with_csr_rw 0 1 0.00
clkmgr_shadow_reg_errors_with_csr_rw 0.750s 2.511us 0 1 0.00
sec_cm_bus_integrity 0 1 0.00
clkmgr_tl_intg_err 0.850s 9.556us 0 1 0.00
sec_cm_meas_clk_bkgn_chk 0 1 0.00
clkmgr_frequency 0.850s 7.604us 0 1 0.00
sec_cm_timeout_clk_bkgn_chk 0 1 0.00
clkmgr_frequency_timeout 0.610s 4.791us 0 1 0.00
sec_cm_meas_config_shadow 1 1 100.00
clkmgr_shadow_reg_errors 1.260s 62.287us 1 1 100.00
sec_cm_idle_intersig_mubi 1 1 100.00
clkmgr_idle_intersig_mubi 1.190s 60.356us 1 1 100.00
sec_cm_jitter_config_mubi 1 1 100.00
clkmgr_csr_rw 0.850s 18.558us 1 1 100.00
sec_cm_idle_ctr_redun 1 1 100.00
clkmgr_sec_cm 5.440s 582.891us 1 1 100.00
sec_cm_meas_config_regwen 1 1 100.00
clkmgr_csr_rw 0.850s 18.558us 1 1 100.00
sec_cm_clk_ctrl_config_regwen 1 1 100.00
clkmgr_csr_rw 0.850s 18.558us 1 1 100.00
prim_count_check 1 1 100.00
clkmgr_sec_cm 5.440s 582.891us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
regwen 0 1 0.00
clkmgr_regwen 0.600s 3.459us 0 1 0.00
stress_all_with_rand_reset 0 1 0.00
clkmgr_stress_all_with_rand_reset 0.920s 5.045us 0 1 0.00