Simulation Results: dma

 
01/12/2025 16:07:45 sha: a49b553 json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 83.79 %
  • code
  • 92.17 %
  • assert
  • 95.97 %
  • func
  • 63.24 %
  • block
  • 97.34 %
  • line
  • 96.85 %
  • branch
  • 95.76 %
  • toggle
  • 83.12 %
  • FSM
  • 92.96 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
unmapped
66.67%
Testpoint Test Max Runtime Sim Time Pass Total %
dma_memory_smoke 1 1 100.00
dma_memory_smoke 7.000s 1670.408us 1 1 100.00
dma_handshake_smoke 1 1 100.00
dma_handshake_smoke 5.000s 605.411us 1 1 100.00
dma_generic_smoke 1 1 100.00
dma_generic_smoke 5.000s 311.690us 1 1 100.00
csr_hw_reset 1 1 100.00
dma_csr_hw_reset 1.000s 18.360us 1 1 100.00
csr_rw 1 1 100.00
dma_csr_rw 1.000s 40.534us 1 1 100.00
csr_bit_bash 1 1 100.00
dma_csr_bit_bash 11.000s 1033.139us 1 1 100.00
csr_aliasing 1 1 100.00
dma_csr_aliasing 7.000s 1757.400us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
dma_csr_mem_rw_with_rand_reset 2.000s 20.907us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
dma_csr_rw 1.000s 40.534us 1 1 100.00
dma_csr_aliasing 7.000s 1757.400us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
dma_memory_region_lock 1 1 100.00
dma_memory_region_lock 45.000s 2341.370us 1 1 100.00
dma_memory_tl_error 1 1 100.00
dma_memory_stress 544.000s 496300.074us 1 1 100.00
dma_handshake_tl_error 1 1 100.00
dma_handshake_stress 335.000s 539453.530us 1 1 100.00
dma_handshake_stress 1 1 100.00
dma_handshake_stress 335.000s 539453.530us 1 1 100.00
dma_memory_stress 1 1 100.00
dma_memory_stress 544.000s 496300.074us 1 1 100.00
dma_generic_stress 1 1 100.00
dma_generic_stress 246.000s 81526.431us 1 1 100.00
dma_handshake_mem_buffer_overflow 1 1 100.00
dma_handshake_stress 335.000s 539453.530us 1 1 100.00
dma_abort 1 1 100.00
dma_abort 6.000s 1158.081us 1 1 100.00
dma_stress_all 1 1 100.00
dma_stress_all 94.000s 29402.808us 1 1 100.00
alert_test 1 1 100.00
dma_alert_test 2.000s 39.792us 1 1 100.00
intr_test 1 1 100.00
dma_intr_test 2.000s 41.691us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
dma_tl_errors 2.000s 85.363us 1 1 100.00
tl_d_illegal_access 1 1 100.00
dma_tl_errors 2.000s 85.363us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
dma_csr_hw_reset 1.000s 18.360us 1 1 100.00
dma_csr_rw 1.000s 40.534us 1 1 100.00
dma_csr_aliasing 7.000s 1757.400us 1 1 100.00
dma_same_csr_outstanding 3.000s 467.507us 1 1 100.00
tl_d_partial_access 4 4 100.00
dma_csr_hw_reset 1.000s 18.360us 1 1 100.00
dma_csr_rw 1.000s 40.534us 1 1 100.00
dma_csr_aliasing 7.000s 1757.400us 1 1 100.00
dma_same_csr_outstanding 3.000s 467.507us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
dma_illegal_addr_range 3 3 100.00
dma_mem_enabled 22.000s 368.171us 1 1 100.00
dma_generic_stress 246.000s 81526.431us 1 1 100.00
dma_handshake_stress 335.000s 539453.530us 1 1 100.00
dma_config_lock 1 1 100.00
dma_config_lock 5.000s 1225.852us 1 1 100.00
tl_intg_err 2 2 100.00
dma_sec_cm 2.000s 11.272us 1 1 100.00
dma_tl_intg_err 3.000s 105.398us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
Unmapped 2 3 66.67
dma_short_transfer 101.000s 11186.001us 1 1 100.00
dma_longer_transfer 5.000s 206.494us 1 1 100.00
dma_stress_all_with_rand_reset 19.000s 4579.088us 0 1 0.00