Simulation Results: edn

 
01/12/2025 16:07:45 sha: a49b553 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 85.74 %
  • code
  • 83.89 %
  • assert
  • 96.22 %
  • func
  • 77.10 %
  • line
  • 97.91 %
  • branch
  • 92.67 %
  • cond
  • 87.74 %
  • toggle
  • 85.34 %
  • FSM
  • 55.81 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
edn_smoke 0.850s 48.297us 1 1 100.00
csr_hw_reset 1 1 100.00
edn_csr_hw_reset 0.770s 36.005us 1 1 100.00
csr_rw 1 1 100.00
edn_csr_rw 0.890s 34.210us 1 1 100.00
csr_bit_bash 1 1 100.00
edn_csr_bit_bash 1.580s 67.519us 1 1 100.00
csr_aliasing 1 1 100.00
edn_csr_aliasing 1.270s 79.964us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
edn_csr_mem_rw_with_rand_reset 1.100s 106.829us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
edn_csr_rw 0.890s 34.210us 1 1 100.00
edn_csr_aliasing 1.270s 79.964us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
firmware 1 1 100.00
edn_genbits 1.160s 44.761us 1 1 100.00
csrng_commands 1 1 100.00
edn_genbits 1.160s 44.761us 1 1 100.00
genbits 1 1 100.00
edn_genbits 1.160s 44.761us 1 1 100.00
interrupts 1 1 100.00
edn_intr 0.760s 37.310us 1 1 100.00
alerts 1 1 100.00
edn_alert 1.010s 95.128us 1 1 100.00
errs 1 1 100.00
edn_err 0.900s 31.328us 1 1 100.00
disable 2 2 100.00
edn_disable 0.780s 12.182us 1 1 100.00
edn_disable_auto_req_mode 0.840s 78.353us 1 1 100.00
stress_all 1 1 100.00
edn_stress_all 1.360s 256.470us 1 1 100.00
intr_test 1 1 100.00
edn_intr_test 0.860s 14.513us 1 1 100.00
alert_test 1 1 100.00
edn_alert_test 0.770s 20.406us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
edn_tl_errors 3.180s 266.541us 1 1 100.00
tl_d_illegal_access 1 1 100.00
edn_tl_errors 3.180s 266.541us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
edn_csr_hw_reset 0.770s 36.005us 1 1 100.00
edn_csr_rw 0.890s 34.210us 1 1 100.00
edn_csr_aliasing 1.270s 79.964us 1 1 100.00
edn_same_csr_outstanding 1.100s 66.886us 1 1 100.00
tl_d_partial_access 4 4 100.00
edn_csr_hw_reset 0.770s 36.005us 1 1 100.00
edn_csr_rw 0.890s 34.210us 1 1 100.00
edn_csr_aliasing 1.270s 79.964us 1 1 100.00
edn_same_csr_outstanding 1.100s 66.886us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
edn_tl_intg_err 1.350s 46.812us 1 1 100.00
edn_sec_cm 3.290s 482.399us 1 1 100.00
sec_cm_config_regwen 1 1 100.00
edn_regwen 0.760s 67.000us 1 1 100.00
sec_cm_config_mubi 1 1 100.00
edn_alert 1.010s 95.128us 1 1 100.00
sec_cm_main_sm_fsm_sparse 1 1 100.00
edn_sec_cm 3.290s 482.399us 1 1 100.00
sec_cm_ack_sm_fsm_sparse 1 1 100.00
edn_sec_cm 3.290s 482.399us 1 1 100.00
sec_cm_fifo_ctr_redun 1 1 100.00
edn_sec_cm 3.290s 482.399us 1 1 100.00
sec_cm_ctr_redun 1 1 100.00
edn_sec_cm 3.290s 482.399us 1 1 100.00
sec_cm_main_sm_ctr_local_esc 2 2 100.00
edn_alert 1.010s 95.128us 1 1 100.00
edn_sec_cm 3.290s 482.399us 1 1 100.00
sec_cm_cs_rdata_bus_consistency 1 1 100.00
edn_alert 1.010s 95.128us 1 1 100.00
sec_cm_tile_link_bus_integrity 1 1 100.00
edn_tl_intg_err 1.350s 46.812us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
edn_stress_all_with_rand_reset 63.070s 21584.548us 1 1 100.00