Simulation Results: hmac

 
01/12/2025 16:07:45 sha: a49b553 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 80.00 %
  • code
  • 98.05 %
  • assert
  • 97.14 %
  • func
  • 44.82 %
  • line
  • 99.79 %
  • branch
  • 99.67 %
  • cond
  • 96.68 %
  • toggle
  • 100.00 %
  • FSM
  • 94.12 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
100.00%
unmapped
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
hmac_smoke 3.510s 4296.539us 1 1 100.00
csr_hw_reset 1 1 100.00
hmac_csr_hw_reset 0.870s 35.121us 1 1 100.00
csr_rw 1 1 100.00
hmac_csr_rw 0.690s 14.397us 1 1 100.00
csr_bit_bash 1 1 100.00
hmac_csr_bit_bash 3.510s 126.161us 1 1 100.00
csr_aliasing 1 1 100.00
hmac_csr_aliasing 4.020s 1384.078us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
hmac_csr_mem_rw_with_rand_reset 1.360s 41.003us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
hmac_csr_rw 0.690s 14.397us 1 1 100.00
hmac_csr_aliasing 4.020s 1384.078us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
long_msg 1 1 100.00
hmac_long_msg 24.400s 2340.061us 1 1 100.00
back_pressure 1 1 100.00
hmac_back_pressure 58.970s 6032.468us 1 1 100.00
test_vectors 6 6 100.00
hmac_test_sha256_vectors 190.270s 6122.541us 1 1 100.00
hmac_test_sha384_vectors 18.760s 248.350us 1 1 100.00
hmac_test_sha512_vectors 366.290s 106999.178us 1 1 100.00
hmac_test_hmac256_vectors 8.020s 569.742us 1 1 100.00
hmac_test_hmac384_vectors 6.540s 818.510us 1 1 100.00
hmac_test_hmac512_vectors 10.880s 368.990us 1 1 100.00
burst_wr 1 1 100.00
hmac_burst_wr 21.540s 8940.335us 1 1 100.00
datapath_stress 1 1 100.00
hmac_datapath_stress 280.970s 5289.317us 1 1 100.00
error 1 1 100.00
hmac_error 66.000s 3624.422us 1 1 100.00
wipe_secret 1 1 100.00
hmac_wipe_secret 73.590s 36959.299us 1 1 100.00
save_and_restore 6 6 100.00
hmac_smoke 3.510s 4296.539us 1 1 100.00
hmac_long_msg 24.400s 2340.061us 1 1 100.00
hmac_back_pressure 58.970s 6032.468us 1 1 100.00
hmac_datapath_stress 280.970s 5289.317us 1 1 100.00
hmac_burst_wr 21.540s 8940.335us 1 1 100.00
hmac_stress_all 207.370s 6046.311us 1 1 100.00
fifo_empty_status_interrupt 11 11 100.00
hmac_smoke 3.510s 4296.539us 1 1 100.00
hmac_long_msg 24.400s 2340.061us 1 1 100.00
hmac_back_pressure 58.970s 6032.468us 1 1 100.00
hmac_datapath_stress 280.970s 5289.317us 1 1 100.00
hmac_wipe_secret 73.590s 36959.299us 1 1 100.00
hmac_test_sha256_vectors 190.270s 6122.541us 1 1 100.00
hmac_test_sha384_vectors 18.760s 248.350us 1 1 100.00
hmac_test_sha512_vectors 366.290s 106999.178us 1 1 100.00
hmac_test_hmac256_vectors 8.020s 569.742us 1 1 100.00
hmac_test_hmac384_vectors 6.540s 818.510us 1 1 100.00
hmac_test_hmac512_vectors 10.880s 368.990us 1 1 100.00
wide_digest_configurable_key_length 14 14 100.00
hmac_smoke 3.510s 4296.539us 1 1 100.00
hmac_long_msg 24.400s 2340.061us 1 1 100.00
hmac_back_pressure 58.970s 6032.468us 1 1 100.00
hmac_datapath_stress 280.970s 5289.317us 1 1 100.00
hmac_burst_wr 21.540s 8940.335us 1 1 100.00
hmac_error 66.000s 3624.422us 1 1 100.00
hmac_wipe_secret 73.590s 36959.299us 1 1 100.00
hmac_test_sha256_vectors 190.270s 6122.541us 1 1 100.00
hmac_test_sha384_vectors 18.760s 248.350us 1 1 100.00
hmac_test_sha512_vectors 366.290s 106999.178us 1 1 100.00
hmac_test_hmac256_vectors 8.020s 569.742us 1 1 100.00
hmac_test_hmac384_vectors 6.540s 818.510us 1 1 100.00
hmac_test_hmac512_vectors 10.880s 368.990us 1 1 100.00
hmac_stress_all 207.370s 6046.311us 1 1 100.00
stress_all 1 1 100.00
hmac_stress_all 207.370s 6046.311us 1 1 100.00
alert_test 1 1 100.00
hmac_alert_test 0.570s 23.657us 1 1 100.00
intr_test 1 1 100.00
hmac_intr_test 0.540s 37.816us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
hmac_tl_errors 2.070s 55.904us 1 1 100.00
tl_d_illegal_access 1 1 100.00
hmac_tl_errors 2.070s 55.904us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
hmac_csr_hw_reset 0.870s 35.121us 1 1 100.00
hmac_csr_rw 0.690s 14.397us 1 1 100.00
hmac_csr_aliasing 4.020s 1384.078us 1 1 100.00
hmac_same_csr_outstanding 1.730s 138.775us 1 1 100.00
tl_d_partial_access 4 4 100.00
hmac_csr_hw_reset 0.870s 35.121us 1 1 100.00
hmac_csr_rw 0.690s 14.397us 1 1 100.00
hmac_csr_aliasing 4.020s 1384.078us 1 1 100.00
hmac_same_csr_outstanding 1.730s 138.775us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
hmac_sec_cm 0.730s 263.878us 1 1 100.00
hmac_tl_intg_err 2.140s 184.490us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
hmac_tl_intg_err 2.140s 184.490us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
write_config_and_secret_key_during_msg_wr 1 1 100.00
hmac_smoke 3.510s 4296.539us 1 1 100.00
stress_reset 1 1 100.00
hmac_stress_reset 1.780s 174.146us 1 1 100.00
stress_all_with_rand_reset 1 1 100.00
hmac_stress_all_with_rand_reset 91.210s 5047.516us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
Unmapped 1 1 100.00
hmac_directed 0.800s 23.133us 1 1 100.00