Simulation Results: i2c

 
01/12/2025 16:07:45 sha: a49b553 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 87.85 %
  • code
  • 82.69 %
  • assert
  • 96.19 %
  • func
  • 84.67 %
  • line
  • 96.72 %
  • branch
  • 93.04 %
  • cond
  • 88.20 %
  • toggle
  • 89.66 %
  • FSM
  • 45.83 %
Validation stages
V1
100.00%
V2
95.92%
V2S
100.00%
V3
0.00%
Testpoint Test Max Runtime Sim Time Pass Total %
host_smoke 1 1 100.00
i2c_host_smoke 20.850s 1857.979us 1 1 100.00
target_smoke 1 1 100.00
i2c_target_smoke 23.040s 2252.924us 1 1 100.00
csr_hw_reset 1 1 100.00
i2c_csr_hw_reset 0.660s 83.650us 1 1 100.00
csr_rw 1 1 100.00
i2c_csr_rw 0.650s 24.983us 1 1 100.00
csr_bit_bash 1 1 100.00
i2c_csr_bit_bash 1.880s 2999.171us 1 1 100.00
csr_aliasing 1 1 100.00
i2c_csr_aliasing 1.370s 184.673us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
i2c_csr_mem_rw_with_rand_reset 1.130s 34.324us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
i2c_csr_rw 0.650s 24.983us 1 1 100.00
i2c_csr_aliasing 1.370s 184.673us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
host_error_intr 1 1 100.00
i2c_host_error_intr 1.150s 105.739us 1 1 100.00
host_stress_all 1 1 100.00
i2c_host_stress_all 762.580s 18597.101us 1 1 100.00
host_maxperf 1 1 100.00
i2c_host_perf 3.330s 1020.411us 1 1 100.00
host_override 1 1 100.00
i2c_host_override 0.690s 53.482us 1 1 100.00
host_fifo_watermark 1 1 100.00
i2c_host_fifo_watermark 35.430s 5560.310us 1 1 100.00
host_fifo_overflow 1 1 100.00
i2c_host_fifo_overflow 50.170s 2586.486us 1 1 100.00
host_fifo_reset 3 3 100.00
i2c_host_fifo_reset_fmt 0.820s 343.574us 1 1 100.00
i2c_host_fifo_fmt_empty 5.380s 1763.724us 1 1 100.00
i2c_host_fifo_reset_rx 2.360s 176.215us 1 1 100.00
host_fifo_full 1 1 100.00
i2c_host_fifo_full 49.100s 3023.931us 1 1 100.00
host_timeout 1 1 100.00
i2c_host_stretch_timeout 8.080s 3325.772us 1 1 100.00
i2c_host_mode_toggle 0 1 0.00
i2c_host_mode_toggle 1.270s 193.521us 0 1 0.00
target_glitch 0 1 0.00
i2c_target_glitch 1.490s 407.840us 0 1 0.00
target_stress_all 1 1 100.00
i2c_target_stress_all 17.870s 67727.694us 1 1 100.00
target_maxperf 1 1 100.00
i2c_target_perf 2.170s 1775.336us 1 1 100.00
target_fifo_empty 2 2 100.00
i2c_target_stress_rd 3.650s 551.417us 1 1 100.00
i2c_target_intr_smoke 3.710s 3803.006us 1 1 100.00
target_fifo_reset 2 2 100.00
i2c_target_fifo_reset_acq 1.000s 345.227us 1 1 100.00
i2c_target_fifo_reset_tx 0.760s 208.699us 1 1 100.00
target_fifo_full 3 3 100.00
i2c_target_stress_wr 389.140s 46821.712us 1 1 100.00
i2c_target_stress_rd 3.650s 551.417us 1 1 100.00
i2c_target_intr_stress_wr 17.770s 14940.262us 1 1 100.00
target_timeout 1 1 100.00
i2c_target_timeout 4.730s 7523.084us 1 1 100.00
target_clock_stretch 1 1 100.00
i2c_target_stretch 34.320s 5952.020us 1 1 100.00
bad_address 1 1 100.00
i2c_target_bad_addr 3.860s 1255.454us 1 1 100.00
target_mode_glitch 1 1 100.00
i2c_target_hrst 1.520s 245.219us 1 1 100.00
target_fifo_watermark 2 2 100.00
i2c_target_fifo_watermarks_acq 1.920s 556.662us 1 1 100.00
i2c_target_fifo_watermarks_tx 1.080s 756.147us 1 1 100.00
host_mode_config_perf 2 2 100.00
i2c_host_perf 3.330s 1020.411us 1 1 100.00
i2c_host_perf_precise 3.370s 317.816us 1 1 100.00
host_mode_clock_stretching 1 1 100.00
i2c_host_stretch_timeout 8.080s 3325.772us 1 1 100.00
target_mode_tx_stretch_ctrl 1 1 100.00
i2c_target_tx_stretch_ctrl 1.680s 170.092us 1 1 100.00
target_mode_nack_generation 3 3 100.00
i2c_target_nack_acqfull 1.980s 574.866us 1 1 100.00
i2c_target_nack_acqfull_addr 1.690s 10021.456us 1 1 100.00
i2c_target_nack_txstretch 1.200s 560.731us 1 1 100.00
host_mode_halt_on_nak 1 1 100.00
i2c_host_may_nack 6.220s 3039.162us 1 1 100.00
target_mode_smbus_maxlen 1 1 100.00
i2c_target_smbus_maxlen 1.760s 1907.981us 1 1 100.00
alert_test 1 1 100.00
i2c_alert_test 0.690s 22.939us 1 1 100.00
intr_test 1 1 100.00
i2c_intr_test 0.630s 16.665us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
i2c_tl_errors 1.600s 44.511us 1 1 100.00
tl_d_illegal_access 1 1 100.00
i2c_tl_errors 1.600s 44.511us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
i2c_csr_hw_reset 0.660s 83.650us 1 1 100.00
i2c_csr_rw 0.650s 24.983us 1 1 100.00
i2c_csr_aliasing 1.370s 184.673us 1 1 100.00
i2c_same_csr_outstanding 0.710s 31.836us 1 1 100.00
tl_d_partial_access 4 4 100.00
i2c_csr_hw_reset 0.660s 83.650us 1 1 100.00
i2c_csr_rw 0.650s 24.983us 1 1 100.00
i2c_csr_aliasing 1.370s 184.673us 1 1 100.00
i2c_same_csr_outstanding 0.710s 31.836us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
i2c_sec_cm 0.790s 62.189us 1 1 100.00
i2c_tl_intg_err 1.660s 253.224us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
i2c_tl_intg_err 1.660s 253.224us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
host_stress_all_with_rand_reset 0 1 0.00
i2c_host_stress_all_with_rand_reset 10.400s 1303.811us 0 1 0.00
target_error_intr 0 1 0.00
i2c_target_unexp_stop 0.930s 134.323us 0 1 0.00
target_stress_all_with_rand_reset 0 1 0.00
i2c_target_stress_all_with_rand_reset 13.620s 1085.132us 0 1 0.00