Simulation Results: lc_ctrl

 
01/12/2025 16:07:45 sha: a49b553 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 90.48 %
  • code
  • 86.78 %
  • assert
  • 95.99 %
  • func
  • 88.67 %
  • line
  • 97.58 %
  • branch
  • 95.91 %
  • cond
  • 79.18 %
  • toggle
  • 82.65 %
  • FSM
  • 78.57 %
Validation stages
V1
100.00%
V2
90.00%
V2S
71.43%
V3
0.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
lc_ctrl_smoke 1.810s 62.993us 1 1 100.00
csr_hw_reset 1 1 100.00
lc_ctrl_csr_hw_reset 0.980s 16.791us 1 1 100.00
csr_rw 1 1 100.00
lc_ctrl_csr_rw 0.970s 29.355us 1 1 100.00
csr_bit_bash 1 1 100.00
lc_ctrl_csr_bit_bash 1.730s 464.408us 1 1 100.00
csr_aliasing 1 1 100.00
lc_ctrl_csr_aliasing 1.100s 17.315us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
lc_ctrl_csr_mem_rw_with_rand_reset 1.180s 41.431us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
lc_ctrl_csr_rw 0.970s 29.355us 1 1 100.00
lc_ctrl_csr_aliasing 1.100s 17.315us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
state_post_trans 1 1 100.00
lc_ctrl_state_post_trans 3.910s 126.606us 1 1 100.00
regwen_during_op 1 1 100.00
lc_ctrl_regwen_during_op 6.740s 1133.245us 1 1 100.00
rand_wr_claim_transition_if 1 1 100.00
lc_ctrl_claim_transition_if 0.780s 11.937us 1 1 100.00
lc_prog_failure 1 1 100.00
lc_ctrl_prog_failure 2.550s 377.756us 1 1 100.00
lc_state_failure 0 1 0.00
lc_ctrl_state_failure 1.780s 9.839us 0 1 0.00
lc_errors 1 1 100.00
lc_ctrl_errors 6.620s 1050.876us 1 1 100.00
security_escalation 5 7 71.43
lc_ctrl_state_failure 1.780s 9.839us 0 1 0.00
lc_ctrl_prog_failure 2.550s 377.756us 1 1 100.00
lc_ctrl_errors 6.620s 1050.876us 1 1 100.00
lc_ctrl_security_escalation 7.110s 1464.468us 1 1 100.00
lc_ctrl_jtag_state_failure 8.810s 500.694us 0 1 0.00
lc_ctrl_jtag_prog_failure 3.140s 109.666us 1 1 100.00
lc_ctrl_jtag_errors 37.240s 24315.321us 1 1 100.00
jtag_access 13 13 100.00
lc_ctrl_jtag_smoke 3.310s 715.453us 1 1 100.00
lc_ctrl_jtag_state_post_trans 8.490s 2140.876us 1 1 100.00
lc_ctrl_jtag_prog_failure 3.140s 109.666us 1 1 100.00
lc_ctrl_jtag_errors 37.240s 24315.321us 1 1 100.00
lc_ctrl_jtag_access 11.140s 824.400us 1 1 100.00
lc_ctrl_jtag_regwen_during_op 21.100s 2112.380us 1 1 100.00
lc_ctrl_jtag_csr_hw_reset 3.110s 119.297us 1 1 100.00
lc_ctrl_jtag_csr_rw 1.970s 314.382us 1 1 100.00
lc_ctrl_jtag_csr_bit_bash 6.180s 2169.419us 1 1 100.00
lc_ctrl_jtag_csr_aliasing 4.010s 2913.909us 1 1 100.00
lc_ctrl_jtag_same_csr_outstanding 1.710s 33.147us 1 1 100.00
lc_ctrl_jtag_csr_mem_rw_with_rand_reset 1.250s 96.557us 1 1 100.00
lc_ctrl_jtag_alert_test 1.590s 368.953us 1 1 100.00
jtag_priority 1 1 100.00
lc_ctrl_jtag_priority 27.430s 2171.360us 1 1 100.00
lc_ctrl_volatile_unlock 1 1 100.00
lc_ctrl_volatile_unlock_smoke 1.040s 172.120us 1 1 100.00
stress_all 0 1 0.00
lc_ctrl_stress_all 73.380s 4459.533us 0 1 0.00
alert_test 1 1 100.00
lc_ctrl_alert_test 0.810s 29.320us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
lc_ctrl_tl_errors 2.490s 177.424us 1 1 100.00
tl_d_illegal_access 1 1 100.00
lc_ctrl_tl_errors 2.490s 177.424us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
lc_ctrl_csr_hw_reset 0.980s 16.791us 1 1 100.00
lc_ctrl_csr_rw 0.970s 29.355us 1 1 100.00
lc_ctrl_csr_aliasing 1.100s 17.315us 1 1 100.00
lc_ctrl_same_csr_outstanding 0.870s 42.925us 1 1 100.00
tl_d_partial_access 4 4 100.00
lc_ctrl_csr_hw_reset 0.980s 16.791us 1 1 100.00
lc_ctrl_csr_rw 0.970s 29.355us 1 1 100.00
lc_ctrl_csr_aliasing 1.100s 17.315us 1 1 100.00
lc_ctrl_same_csr_outstanding 0.870s 42.925us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
lc_ctrl_sec_cm 6.290s 138.704us 1 1 100.00
lc_ctrl_tl_intg_err 2.730s 505.830us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
lc_ctrl_tl_intg_err 2.730s 505.830us 1 1 100.00
sec_cm_transition_config_regwen 1 1 100.00
lc_ctrl_regwen_during_op 6.740s 1133.245us 1 1 100.00
sec_cm_manuf_state_sparse 1 2 50.00
lc_ctrl_state_failure 1.780s 9.839us 0 1 0.00
lc_ctrl_sec_cm 6.290s 138.704us 1 1 100.00
sec_cm_transition_ctr_sparse 1 2 50.00
lc_ctrl_state_failure 1.780s 9.839us 0 1 0.00
lc_ctrl_sec_cm 6.290s 138.704us 1 1 100.00
sec_cm_manuf_state_bkgn_chk 1 2 50.00
lc_ctrl_state_failure 1.780s 9.839us 0 1 0.00
lc_ctrl_sec_cm 6.290s 138.704us 1 1 100.00
sec_cm_transition_ctr_bkgn_chk 1 2 50.00
lc_ctrl_state_failure 1.780s 9.839us 0 1 0.00
lc_ctrl_sec_cm 6.290s 138.704us 1 1 100.00
sec_cm_state_config_sparse 1 2 50.00
lc_ctrl_state_failure 1.780s 9.839us 0 1 0.00
lc_ctrl_sec_cm 6.290s 138.704us 1 1 100.00
sec_cm_main_fsm_sparse 1 2 50.00
lc_ctrl_state_failure 1.780s 9.839us 0 1 0.00
lc_ctrl_sec_cm 6.290s 138.704us 1 1 100.00
sec_cm_kmac_fsm_sparse 1 2 50.00
lc_ctrl_state_failure 1.780s 9.839us 0 1 0.00
lc_ctrl_sec_cm 6.290s 138.704us 1 1 100.00
sec_cm_main_fsm_local_esc 1 2 50.00
lc_ctrl_state_failure 1.780s 9.839us 0 1 0.00
lc_ctrl_sec_cm 6.290s 138.704us 1 1 100.00
sec_cm_main_fsm_global_esc 1 1 100.00
lc_ctrl_security_escalation 7.110s 1464.468us 1 1 100.00
sec_cm_main_ctrl_flow_consistency 2 2 100.00
lc_ctrl_state_post_trans 3.910s 126.606us 1 1 100.00
lc_ctrl_jtag_state_post_trans 8.490s 2140.876us 1 1 100.00
sec_cm_intersig_mubi 1 1 100.00
lc_ctrl_sec_mubi 5.410s 228.317us 1 1 100.00
sec_cm_token_valid_ctrl_mubi 1 1 100.00
lc_ctrl_sec_mubi 5.410s 228.317us 1 1 100.00
sec_cm_token_digest 1 1 100.00
lc_ctrl_sec_token_digest 5.800s 2436.225us 1 1 100.00
sec_cm_token_mux_ctrl_redun 1 1 100.00
lc_ctrl_sec_token_mux 6.200s 405.765us 1 1 100.00
sec_cm_token_valid_mux_redun 1 1 100.00
lc_ctrl_sec_token_mux 6.200s 405.765us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 0 1 0.00
lc_ctrl_stress_all_with_rand_reset 2.660s 57.154us 0 1 0.00