Simulation Results: lc_ctrl

 
01/12/2025 16:07:45 sha: a49b553 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 91.16 %
  • code
  • 86.84 %
  • assert
  • 95.99 %
  • func
  • 90.65 %
  • line
  • 97.45 %
  • branch
  • 95.38 %
  • cond
  • 79.07 %
  • toggle
  • 83.25 %
  • FSM
  • 79.07 %
Validation stages
V1
100.00%
V2
90.00%
V2S
71.43%
V3
0.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
lc_ctrl_smoke 1.040s 24.409us 1 1 100.00
csr_hw_reset 1 1 100.00
lc_ctrl_csr_hw_reset 0.750s 20.307us 1 1 100.00
csr_rw 1 1 100.00
lc_ctrl_csr_rw 0.700s 55.801us 1 1 100.00
csr_bit_bash 1 1 100.00
lc_ctrl_csr_bit_bash 2.090s 66.714us 1 1 100.00
csr_aliasing 1 1 100.00
lc_ctrl_csr_aliasing 1.070s 428.126us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
lc_ctrl_csr_mem_rw_with_rand_reset 1.210s 54.470us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
lc_ctrl_csr_rw 0.700s 55.801us 1 1 100.00
lc_ctrl_csr_aliasing 1.070s 428.126us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
state_post_trans 1 1 100.00
lc_ctrl_state_post_trans 5.860s 140.077us 1 1 100.00
regwen_during_op 1 1 100.00
lc_ctrl_regwen_during_op 3.680s 320.503us 1 1 100.00
rand_wr_claim_transition_if 1 1 100.00
lc_ctrl_claim_transition_if 1.040s 38.341us 1 1 100.00
lc_prog_failure 1 1 100.00
lc_ctrl_prog_failure 2.720s 357.378us 1 1 100.00
lc_state_failure 0 1 0.00
lc_ctrl_state_failure 3.470s 32.046us 0 1 0.00
lc_errors 1 1 100.00
lc_ctrl_errors 7.970s 533.149us 1 1 100.00
security_escalation 5 7 71.43
lc_ctrl_state_failure 3.470s 32.046us 0 1 0.00
lc_ctrl_prog_failure 2.720s 357.378us 1 1 100.00
lc_ctrl_errors 7.970s 533.149us 1 1 100.00
lc_ctrl_security_escalation 4.380s 2150.030us 1 1 100.00
lc_ctrl_jtag_state_failure 6.700s 950.529us 0 1 0.00
lc_ctrl_jtag_prog_failure 4.150s 232.510us 1 1 100.00
lc_ctrl_jtag_errors 54.510s 3091.025us 1 1 100.00
jtag_access 13 13 100.00
lc_ctrl_jtag_smoke 3.860s 179.947us 1 1 100.00
lc_ctrl_jtag_state_post_trans 15.120s 685.987us 1 1 100.00
lc_ctrl_jtag_prog_failure 4.150s 232.510us 1 1 100.00
lc_ctrl_jtag_errors 54.510s 3091.025us 1 1 100.00
lc_ctrl_jtag_access 6.400s 1446.330us 1 1 100.00
lc_ctrl_jtag_regwen_during_op 11.450s 1378.106us 1 1 100.00
lc_ctrl_jtag_csr_hw_reset 2.290s 1118.529us 1 1 100.00
lc_ctrl_jtag_csr_rw 1.670s 216.774us 1 1 100.00
lc_ctrl_jtag_csr_bit_bash 8.440s 995.200us 1 1 100.00
lc_ctrl_jtag_csr_aliasing 22.690s 1493.269us 1 1 100.00
lc_ctrl_jtag_same_csr_outstanding 1.630s 66.178us 1 1 100.00
lc_ctrl_jtag_csr_mem_rw_with_rand_reset 3.500s 876.675us 1 1 100.00
lc_ctrl_jtag_alert_test 1.880s 315.449us 1 1 100.00
jtag_priority 1 1 100.00
lc_ctrl_jtag_priority 7.960s 417.901us 1 1 100.00
lc_ctrl_volatile_unlock 1 1 100.00
lc_ctrl_volatile_unlock_smoke 1.180s 15.019us 1 1 100.00
stress_all 0 1 0.00
lc_ctrl_stress_all 16.800s 1277.099us 0 1 0.00
alert_test 1 1 100.00
lc_ctrl_alert_test 1.100s 72.722us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
lc_ctrl_tl_errors 1.600s 231.289us 1 1 100.00
tl_d_illegal_access 1 1 100.00
lc_ctrl_tl_errors 1.600s 231.289us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
lc_ctrl_csr_hw_reset 0.750s 20.307us 1 1 100.00
lc_ctrl_csr_rw 0.700s 55.801us 1 1 100.00
lc_ctrl_csr_aliasing 1.070s 428.126us 1 1 100.00
lc_ctrl_same_csr_outstanding 1.230s 28.914us 1 1 100.00
tl_d_partial_access 4 4 100.00
lc_ctrl_csr_hw_reset 0.750s 20.307us 1 1 100.00
lc_ctrl_csr_rw 0.700s 55.801us 1 1 100.00
lc_ctrl_csr_aliasing 1.070s 428.126us 1 1 100.00
lc_ctrl_same_csr_outstanding 1.230s 28.914us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
lc_ctrl_sec_cm 5.860s 712.959us 1 1 100.00
lc_ctrl_tl_intg_err 1.790s 173.514us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
lc_ctrl_tl_intg_err 1.790s 173.514us 1 1 100.00
sec_cm_transition_config_regwen 1 1 100.00
lc_ctrl_regwen_during_op 3.680s 320.503us 1 1 100.00
sec_cm_manuf_state_sparse 1 2 50.00
lc_ctrl_state_failure 3.470s 32.046us 0 1 0.00
lc_ctrl_sec_cm 5.860s 712.959us 1 1 100.00
sec_cm_transition_ctr_sparse 1 2 50.00
lc_ctrl_state_failure 3.470s 32.046us 0 1 0.00
lc_ctrl_sec_cm 5.860s 712.959us 1 1 100.00
sec_cm_manuf_state_bkgn_chk 1 2 50.00
lc_ctrl_state_failure 3.470s 32.046us 0 1 0.00
lc_ctrl_sec_cm 5.860s 712.959us 1 1 100.00
sec_cm_transition_ctr_bkgn_chk 1 2 50.00
lc_ctrl_state_failure 3.470s 32.046us 0 1 0.00
lc_ctrl_sec_cm 5.860s 712.959us 1 1 100.00
sec_cm_state_config_sparse 1 2 50.00
lc_ctrl_state_failure 3.470s 32.046us 0 1 0.00
lc_ctrl_sec_cm 5.860s 712.959us 1 1 100.00
sec_cm_main_fsm_sparse 1 2 50.00
lc_ctrl_state_failure 3.470s 32.046us 0 1 0.00
lc_ctrl_sec_cm 5.860s 712.959us 1 1 100.00
sec_cm_kmac_fsm_sparse 1 2 50.00
lc_ctrl_state_failure 3.470s 32.046us 0 1 0.00
lc_ctrl_sec_cm 5.860s 712.959us 1 1 100.00
sec_cm_main_fsm_local_esc 1 2 50.00
lc_ctrl_state_failure 3.470s 32.046us 0 1 0.00
lc_ctrl_sec_cm 5.860s 712.959us 1 1 100.00
sec_cm_main_fsm_global_esc 1 1 100.00
lc_ctrl_security_escalation 4.380s 2150.030us 1 1 100.00
sec_cm_main_ctrl_flow_consistency 2 2 100.00
lc_ctrl_state_post_trans 5.860s 140.077us 1 1 100.00
lc_ctrl_jtag_state_post_trans 15.120s 685.987us 1 1 100.00
sec_cm_intersig_mubi 1 1 100.00
lc_ctrl_sec_mubi 6.230s 261.620us 1 1 100.00
sec_cm_token_valid_ctrl_mubi 1 1 100.00
lc_ctrl_sec_mubi 6.230s 261.620us 1 1 100.00
sec_cm_token_digest 1 1 100.00
lc_ctrl_sec_token_digest 10.950s 840.543us 1 1 100.00
sec_cm_token_mux_ctrl_redun 1 1 100.00
lc_ctrl_sec_token_mux 7.780s 1516.776us 1 1 100.00
sec_cm_token_valid_mux_redun 1 1 100.00
lc_ctrl_sec_token_mux 7.780s 1516.776us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 0 1 0.00
lc_ctrl_stress_all_with_rand_reset 3.070s 218.452us 0 1 0.00