Simulation Results: rom_ctrl

 
01/12/2025 16:07:45 sha: a49b553 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 96.80 %
  • code
  • 97.89 %
  • assert
  • 96.80 %
  • func
  • 95.70 %
  • line
  • 99.46 %
  • branch
  • 98.91 %
  • cond
  • 97.77 %
  • toggle
  • 100.00 %
  • FSM
  • 93.33 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
rom_ctrl_smoke 5.040s 179.442us 1 1 100.00
csr_hw_reset 1 1 100.00
rom_ctrl_csr_hw_reset 6.530s 176.047us 1 1 100.00
csr_rw 1 1 100.00
rom_ctrl_csr_rw 3.280s 958.051us 1 1 100.00
csr_bit_bash 1 1 100.00
rom_ctrl_csr_bit_bash 5.360s 173.508us 1 1 100.00
csr_aliasing 1 1 100.00
rom_ctrl_csr_aliasing 3.370s 399.364us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
rom_ctrl_csr_mem_rw_with_rand_reset 4.650s 156.382us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
rom_ctrl_csr_rw 3.280s 958.051us 1 1 100.00
rom_ctrl_csr_aliasing 3.370s 399.364us 1 1 100.00
mem_walk 1 1 100.00
rom_ctrl_mem_walk 6.440s 164.750us 1 1 100.00
mem_partial_access 1 1 100.00
rom_ctrl_mem_partial_access 3.860s 123.775us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
max_throughput_chk 1 1 100.00
rom_ctrl_max_throughput_chk 3.810s 408.068us 1 1 100.00
stress_all 1 1 100.00
rom_ctrl_stress_all 10.050s 1182.009us 1 1 100.00
kmac_err_chk 1 1 100.00
rom_ctrl_kmac_err_chk 6.680s 4210.048us 1 1 100.00
alert_test 1 1 100.00
rom_ctrl_alert_test 3.370s 1161.296us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
rom_ctrl_tl_errors 6.100s 543.801us 1 1 100.00
tl_d_illegal_access 1 1 100.00
rom_ctrl_tl_errors 6.100s 543.801us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
rom_ctrl_csr_hw_reset 6.530s 176.047us 1 1 100.00
rom_ctrl_csr_rw 3.280s 958.051us 1 1 100.00
rom_ctrl_csr_aliasing 3.370s 399.364us 1 1 100.00
rom_ctrl_same_csr_outstanding 4.460s 533.974us 1 1 100.00
tl_d_partial_access 4 4 100.00
rom_ctrl_csr_hw_reset 6.530s 176.047us 1 1 100.00
rom_ctrl_csr_rw 3.280s 958.051us 1 1 100.00
rom_ctrl_csr_aliasing 3.370s 399.364us 1 1 100.00
rom_ctrl_same_csr_outstanding 4.460s 533.974us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
corrupt_sig_fatal_chk 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 62.420s 23594.057us 1 1 100.00
passthru_mem_tl_intg_err 1 1 100.00
rom_ctrl_passthru_mem_tl_intg_err 11.450s 2583.189us 1 1 100.00
tl_intg_err 2 2 100.00
rom_ctrl_sec_cm 97.580s 635.891us 1 1 100.00
rom_ctrl_tl_intg_err 42.600s 855.042us 1 1 100.00
prim_fsm_check 1 1 100.00
rom_ctrl_sec_cm 97.580s 635.891us 1 1 100.00
prim_count_check 1 1 100.00
rom_ctrl_sec_cm 97.580s 635.891us 1 1 100.00
sec_cm_checker_ctr_consistency 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 62.420s 23594.057us 1 1 100.00
sec_cm_checker_ctrl_flow_consistency 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 62.420s 23594.057us 1 1 100.00
sec_cm_checker_fsm_local_esc 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 62.420s 23594.057us 1 1 100.00
sec_cm_compare_ctrl_flow_consistency 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 62.420s 23594.057us 1 1 100.00
sec_cm_compare_ctr_consistency 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 62.420s 23594.057us 1 1 100.00
sec_cm_compare_ctr_redun 1 1 100.00
rom_ctrl_sec_cm 97.580s 635.891us 1 1 100.00
sec_cm_fsm_sparse 1 1 100.00
rom_ctrl_sec_cm 97.580s 635.891us 1 1 100.00
sec_cm_mem_scramble 1 1 100.00
rom_ctrl_smoke 5.040s 179.442us 1 1 100.00
sec_cm_mem_digest 1 1 100.00
rom_ctrl_smoke 5.040s 179.442us 1 1 100.00
sec_cm_intersig_mubi 1 1 100.00
rom_ctrl_smoke 5.040s 179.442us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
rom_ctrl_tl_intg_err 42.600s 855.042us 1 1 100.00
sec_cm_bus_local_esc 2 2 100.00
rom_ctrl_corrupt_sig_fatal_chk 62.420s 23594.057us 1 1 100.00
rom_ctrl_kmac_err_chk 6.680s 4210.048us 1 1 100.00
sec_cm_mux_mubi 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 62.420s 23594.057us 1 1 100.00
sec_cm_mux_consistency 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 62.420s 23594.057us 1 1 100.00
sec_cm_ctrl_redun 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 62.420s 23594.057us 1 1 100.00
sec_cm_ctrl_mem_integrity 1 1 100.00
rom_ctrl_passthru_mem_tl_intg_err 11.450s 2583.189us 1 1 100.00
sec_cm_tlul_fifo_ctr_redun 1 1 100.00
rom_ctrl_sec_cm 97.580s 635.891us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
rom_ctrl_stress_all_with_rand_reset 106.930s 2690.194us 1 1 100.00